System Management Bus (SMBus) Specification Version 3.1
© 2018 System Management Interface Forum, Inc. 5 of 85
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Table of Tables
Table 1. Transaction protocol diagram symbols and elements .................................................................. 11
Table 2. SMBus AC specifications .............................................................................................................. 17
Table 3. Low Power SMBus DC specification ............................................................................................. 23
Table 4. High Power SMBus DC specification ............................................................................................ 25
Table 5: UDID bit fields descriptions ........................................................................................................... 48
Table 6: 8-bit device capabilities field descriptions ..................................................................................... 49
Table 7: Version/Revision bit fields description .......................................................................................... 49
Table 8: Interface field bit fields description ................................................................................................ 50
Table 9. Internal state of ARP-capable devices on Power-On Reset ......................................................... 52
Table 10. ARP command number scheme ................................................................................................. 53
Table 11. SMBus device characterizations ................................................................................................. 53
Table 12. Device decodes of AV and AR flags ........................................................................................... 64
Table 13.
SMBus Suspend parameters ...................................................................................................... 70
Table 14. Selected parameter differences between Standard-Mode I²C and 100 kHz Class SMBus ....... 74
Table 15. DC parameter differences between Fast-mode I²C and 400 kHz Class SMBus
................. 75
Table 16. DC parameter differences between Fast-mode Plus I²C and 1 MHz Class SMBus
........... 76
Table 17. Reserved and pre-assigned SMBus addresses ......................................................................... 79
Table of Figures
Figure 1: Generic transaction diagram ........................................................................................................ 13
Figure 2: SMBus Topology .......................................................................................................................... 14
Figure 3: SMBus pull-up circuitry ................................................................................................................ 14
Figure 4: Example input and output stages of SMBus devices .................................................................. 15
Figure 5. SMBus timing measurements ...................................................................................................... 17
Figure 6. Timeout intervals .......................................................................................................................... 20
Figure 7: Clock extension measurement intervals ...................................................................................... 21
Figure 8:
SMBus branch with multiple devices attached
......................................................................... 22
Figure 9:
SMBus circuit model
.................................................................................................................. 23
Figure 10: Data validity ............................................................................................................................... 27
Figure 11: START and STOP conditions .................................................................................................... 27
Figure 12: SMBus byte format .................................................................................................................... 28
Figure 13:
ACK signaling of SMBus
.......................................................................................................... 28
Figure 14. NACK signaling on SMBus ........................................................................................................ 29
Figure 15: SMBus clock synchronization .................................................................................................... 30
Figure 16: SMBus arbitration
.................................................................................................................... 31
Figure 17: Periodic clock stretching by a slave SMBus device
.............................................................. 32
Figure 18: Random clock stretching
......................................................................................................... 33
Figure 19: Data transfer over SMBus
...................................................................................................... 33
Figure 20: Quick Command protocol
....................................................................................................... 38
Figure 21: Send Byte protocol
.................................................................................................................. 39
Figure 22: Send Byte protocol with PEC ..................................................................................................... 39
Figure 23: Receive Byte protocol
............................................................................................................. 39
Figure 24: Receive Byte protocol with PEC
............................................................................................. 39
Figure 25: Write Byte protocol
.................................................................................................................. 39
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