SX1301数据手册_sx1301数据手册

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SX1301

WIRELESS, SENSING & TIMING Datasheet

V2.01 June 2014 1

DDR - LoRa

LoRa

(G)FSK

(G)FSK/LoRa

Packet handler

MCU

SX1301

SPI

Packet

handler

Control

Tx/Rx

(Tx/Rx)

(GPS)

I/Q

timestamp

General Description

The SX1301 digital baseband chip is a massive

digital signal processing engine specifically

designed to offer breakthrough gateway

capabilities in the ISM bands worldwide. It

integrates the LoRa concentrator IP.

The LoRa concentrator is a multi-channel high

performance transmitter/receiver designed to

simultaneously receive several LoRa packets

using random spreading factors on random

channels. Its goal is to enable robust

connection between a central wireless data

concentrator and a massive amount of

wireless end-points spread over a very wide

range of distances.

The SX1301 is targeted at smart metering

fixed networks and Internet of Things

applications with up to 5000 nodes per km2 in

moderately interfered environment.

Ordering Information

Part Number

Conditioning

SX1301IMLTRC

Tape & Reel

3,000 parts per reel

SX1301IMLT

Trays

Key product features

 Up to -142.5 dBm sensitivity with SX1257

or SX1255 Tx/Rx front-end

 -140 dBm with included ref

design

 70 dB CW interferer rejection at

1 MHz offset

 Able to operate with negative SNR

 CCR up to 9 dB

 Emulates 49x LoRa demodulators and 1x

(G)FSK demodulator

 Dual digital Tx & Rx radio front-end

interfaces

 10 programmable parallel demodulation

paths

 Dynamic data-rate adaptation (ADR)

 True antenna diversity or simultaneous

dual-band operation

Applications

 Smart Metering

 Security Sensors Network

 Agricultural Monitoring

 Internet of Things (IoT)

SX1301

WIRELESS, SENSING & TIMING Datasheet

V2.01 June 2014 2

Contents

1 PIN CONFIGURATION .................................................................................................................. 7

1.1 Pins placement and circuit marking ............................................................................................ 7

1.2 Pins description ........................................................................................................................... 8

2 ELECTRICAL CHARACTERISTICS ................................................................................................. 10

2.1 Absolute maximum ratings ....................................................................................................... 10

2.2 Constraints on external ............................................................................................................. 10

2.3 Operating conditions ................................................................................................................ 10

2.4 Electrical specifications ............................................................................................................. 11

2.5 Timing specifications ................................................................................................................. 11

3 CIRCUIT OPERATION ................................................................................................................. 12

3.1 General Presentation ................................................................................................................ 12

3.2 Power-on ................................................................................................................................... 12

3.2.1 Power-up sequence .............................................................................................................. 12

3.2.2 Setting the circuit is low-power mode .................................................................................. 12

3.3 Clocking ..................................................................................................................................... 13

3.4 SPI Interface .............................................................................................................................. 14

3.5 Rx I/Q Interface ......................................................................................................................... 15

3.5.1 I/Q generated on clock rising edge ....................................................................................... 15

3.5.2 I/Q generated on clock falling edge ...................................................................................... 15

3.6 GPIO mapping ........................................................................................................................... 16

3.6.1 GPIO output configuration .................................................................................................... 16

3.6.2 GPIO input configuration ...................................................................................................... 16

3.7 RX mode block diagram, reception paths characteristics ......................................................... 17

3.7.1 Block diagram ........................................................................................................................ 17

3.7.2 Reception paths characteristics ............................................................................................ 17

3.8 Packet engine and data buffers ................................................................................................ 19

3.8.1 Receiver Packet engine ......................................................................................................... 19

3.8.2 Transmitter packet engine .................................................................................................... 21

3.9 Receiver IF frequencies configuration ...................................................................................... 23

3.9.1 Configuration using 2 x SX1257 radios .................................................................................. 23

3.9.2 Two SX1255 : 433 MHz band ................................................................................................ 25

3.9.3 One SX1257 and one SX1255 ................................................................................................ 25

3.10 Connection to RF front-end ...................................................................................................... 26

3.10.1 Connection to Semtech SX1255 or SX1257 components ..................................................... 26

3.10.2 SX1301 RX operation using a third party RF front-end ......................................................... 27

3.10.3 Radio calibration ................................................................................................................... 29

3.10.4 SX1301 connection to RF front-end for TX operation........................................................... 29

3.11 Reference application ............................................................................................................... 30

3.12 SX1301 sensitivity performance in reference application ........................................................ 31

3.13 SX1301 sensitivity vs data rate in LoRa mode........................................................................... 31

3.13.1 125kHz mode: IF8, IF[0 to 7] paths ....................................................................................... 31

3.13.2 250 & 500 kHz mode: IF8 only .............................................................................................. 32

3.14 SX1301 interference rejection .................................................................................................. 32

3.15 Hardware Abstraction Layer (HAL) ........................................................................................... 34

3.15.1 Introduction .......................................................................................................................... 34

3.15.2 Abstraction presented to the gateway host ......................................................................... 34

SX1301

WIRELESS, SENSING & TIMING Datasheet

V2.01 June 2014 3

3.15.3 Composition of the software library ..................................................................................... 36

3.15.4 Interaction with the Lora hardware ...................................................................................... 37

3.15.5 Important HAL functions ....................................................................................................... 39

4 MEMORY MAP .......................................................................................................................... 40

4.1 Registers list .............................................................................................................................. 40

4.2 Registers Description ................................................................................................................ 43

4.2.1 All pages registers ................................................................................................................. 43

4.2.2 Page 0 registers ..................................................................................................................... 45

4.2.3 Page 1 registers ..................................................................................................................... 48

4.2.4 Page 2 registers ..................................................................................................................... 51

5 EXTERNAL COMPONENTS ......................................................................................................... 54

6 PCB LAYOUT CONSIDERATIONS ................................................................................................ 55

7 PACKAGING INFORMATION ...................................................................................................... 58

7.1 Package Outline Drawing .......................................................................................................... 58

7.2 Thermal impedance of package ................................................................................................ 58

7.3 Land Pattern Drawing ............................................................................................................... 59

8 REVISION INFORMATION .......................................................................................................... 60

Figures

Figure 1 Top view of SX1301 package with 64 pins and exposed ground paddle (bottom of package). 7

Figure 2 Power-up sequence ................................................................................................................ 12

Figure 3 SPI Timing Diagram (single access) ......................................................................................... 14

Figure 4 I/Q on clock rising edge ........................................................................................................... 15

Figure 5 I/Q on clock falling edge.......................................................................................................... 15

Figure 6 SX1301 digital baseband chip block diagram .......................................................................... 17

Figure 7 Access FIFO and data buffer.................................................................................................... 20

Figure 8 SX1255/57 digital I/Q power spectral density ........................................................................ 23

Figure 9 Radio spectrum ....................................................................................................................... 24

Figure 10 Radio spectrum ..................................................................................................................... 25

Figure 11 Radio spectrum ..................................................................................................................... 26

Figure 12 Dual band operation ............................................................................................................. 27

Figure 13 SX1301 with third party frontend ......................................................................................... 28

Figure 14 Digital interface for third party radio .................................................................................... 28

Figure 15 Transmission schematics ...................................................................................................... 29

Figure 16 Reference application ........................................................................................................... 30

Figure 17 CW interferer rejection @ SF7 .............................................................................................. 33

Figure 18 CW interferer rejection @ SF12 ............................................................................................ 33

Figure 19 EPCOS B3117 SAW filter transfer function ........................................................................... 34

Figure 20 PCB layout example .............................................................................................................. 57

Figure 21 Package dimensions .............................................................................................................. 58

Figure 22 Land pattern drawing ............................................................................................................ 59

Tables

Table 1 Pins name and description ......................................................................................................... 9

Table 2 Absolute maximum ratings ...................................................................................................... 10

SX1301

WIRELESS, SENSING & TIMING Datasheet

V2.01 June 2014 4

Table 3 Externals ................................................................................................................................... 10

Table 4 Operating conditions for electrical specifications .................................................................... 10

Table 5 Electrical specifications ............................................................................................................ 11

Table 6 Timing specifications ................................................................................................................ 11

Table 6 GPIO output configuration ....................................................................................................... 16

Table 6 GPIO input configuration ......................................................................................................... 16

Table 7 Packet data fields ..................................................................................................................... 21

Table 8 Packet structure for transmission ............................................................................................ 23

Table 9 IF frequencies set ..................................................................................................................... 24

Table 10 IF frequency used ................................................................................................................... 25

Table 11 SX1301 performance in reference application ...................................................................... 31

Table 12 Sensitivity with 125 kHz mode ............................................................................................... 31

Table 13 Sensitivity with 250 kHz mode ............................................................................................... 32

Table 14 Sensitivity with 500 kHz mode ............................................................................................... 32

Table 15 HAL main functions ................................................................................................................ 39

Table 16 List of registers that are accessed without paging ................................................................. 40

Table 17 List of registers on page 0 ...................................................................................................... 41

Table 18 List of registers on page 1 ...................................................................................................... 42

Table 19 List of registers on page 2 ...................................................................................................... 43

Table 20 RegPage definition ................................................................................................................. 43

Table 21 RegVer definition.................................................................................................................... 43

Table 22 RegRdbal definition ................................................................................................................ 43

Table 23 RegRdbah definition ............................................................................................................... 43

Table 24 RegRdbd definition ................................................................................................................. 43

Table 25 RegTdba definition ................................................................................................................. 44

Table 26 RegTdbd definition ................................................................................................................. 44

Table 27 RegMpd definition .................................................................................................................. 44

Table 28 RegRpns definition ................................................................................................................. 44

Table 29 RegRpapl definition ................................................................................................................ 44

Table 30 RegRpaph definition ............................................................................................................... 44

Table 31 RegRps definition ................................................................................................................... 44

Table 32 RegRpps definition ................................................................................................................. 44

Table 33 RegGen definition ................................................................................................................... 44

Table 34 RegCken definition ................................................................................................................. 44

Table 35 RegGpsi definition .................................................................................................................. 44

Table 36 RegGpso definition ................................................................................................................. 45

Table 37 RegGpmode definition ........................................................................................................... 45

Table 38 RegGpregi definition .............................................................................................................. 45

Table 39 RegGprego definition ............................................................................................................. 45

Table 40 RegAgcsts definition ............................................................................................................... 45

Table 41 RegArbsts definition ............................................................................................................... 45

Table 42 RegId definition ...................................................................................................................... 45

Table 43 RegIqcfg definition ................................................................................................................. 45

Table 44 RegDeccfg definition .............................................................................................................. 45

Table 45 RegChrs definition .................................................................................................................. 45

Table 46 RegIf0l definition .................................................................................................................... 45

Table 47 RegIf0h definition ................................................................................................................... 45

Table 48 RegIf1l definition .................................................................................................................... 45

Table 49 RegIf1h definition ................................................................................................................... 46

SX1301

WIRELESS, SENSING & TIMING Datasheet

V2.01 June 2014 5

Table 50 RegIf2l definition .................................................................................................................... 46

Table 51 RegIf2h definition ................................................................................................................... 46

Table 52 RegIf3l definition .................................................................................................................... 46

Table 53 RegIf3h definition ................................................................................................................... 46

Table 54 RegIf4l definition .................................................................................................................... 46

Table 55 RegIf4h definition ................................................................................................................... 46

Table 56 RegIf5l definition .................................................................................................................... 46

Table 57 RegIf5h definition ................................................................................................................... 46

Table 58 RegIf6l definition .................................................................................................................... 46

Table 59 RegIf6h definition ................................................................................................................... 46

Table 60 RefIf7l definition ..................................................................................................................... 46

Table 61 RegIf7h definition ................................................................................................................... 46

Table 62 RegIf8l definition .................................................................................................................... 46

Table 63 RegIf8h definition ................................................................................................................... 46

Table 64 RegIf9l definition .................................................................................................................... 46

Table 65 RegIf9h definition ................................................................................................................... 47

Table 66 RegCore0deten definition ...................................................................................................... 47

Table 67 RegCore1deten definition ...................................................................................................... 47

Table 68 RegCore2deten definition ...................................................................................................... 47

Table 69 RegCore3deten definition ...................................................................................................... 47

Table 70 RegCore4deten definition ...................................................................................................... 47

Table 71 RegCore5deten definition ...................................................................................................... 47

Table 72 RegCore6deten definition ...................................................................................................... 47

Table 73 RegCore7deten definition ...................................................................................................... 47

Table 74 RegAmso124h definition ........................................................................................................ 47

Table 75 RegTimtrak2 definition ........................................................................................................... 47

Table 76 RegPrsymbnbl definition ........................................................................................................ 47

Table 77 RegSymbnbh definition .......................................................................................................... 47

Table 78 RegMisc_cfg2 definition ......................................................................................................... 47

Table 79 RegHeader_cfg1 definition..................................................................................................... 48

Table 80 RegHeader_cfg2 definition..................................................................................................... 48

Table 81 RegMcu_ctrl definition ........................................................................................................... 48

Table 82 RegChann_select_rssi definition ............................................................................................ 48

Table 83 RegTrig definition ................................................................................................................... 48

Table 84 RegTx_offset_i definition ....................................................................................................... 48

Table 85 RegTx_offset_q definition ...................................................................................................... 48

Table 86 RegBhimpcfg1 definition ........................................................................................................ 48

Table 87 RegBhimpcfg2 definition ........................................................................................................ 48

Table 88 RegBhsyncpos definition ........................................................................................................ 49

Table 89 RegBhprsymnbl definition ...................................................................................................... 49

Table 90 RegMbwssf_misc_cfg1 definition .......................................................................................... 49

Table 91 RegMbwssf_misc_cfg2 definition .......................................................................................... 49

Table 92 RegMbwssf_misc_cfg3 definition .......................................................................................... 49

Table 93 RegMbwssf_misc_cfg4 definition .......................................................................................... 49

Table 94 RegTx_status definition .......................................................................................................... 49

Table 95 RegFsx_cfg definition ............................................................................................................. 49

Table 96 RegFsk_cfg2 definition ........................................................................................................... 49

Table 97 RegFsk_error_osr_tol definition ............................................................................................ 50

Table 98 RegFsk_br_ratiol definition .................................................................................................... 50

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2019-02-11

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