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The RISC-V Instruction Set Manual Volume II: Privileged Architec...
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This is version 1.10 of the RISC-V privileged architecture proposal
The RISC-V Instruction Set Manual
Volume II: Privileged Architecture
Privileged Architecture Version 1.10
Document Version 1.10
Warning! This draft speciﬁcation may change before being accepted as
standard by the RISC-V Foundation. While the editors intend future changes
to this speciﬁcation to be forward compatible, it remains possible that
implementations made to this draft speciﬁcation will not conform to the future
Editors: Andrew Waterman
, Krste Asanovi´c
CS Division, EECS Department, University of California, Berkeley
May 7, 2017
Contributors to all versions of the spec in alphabetical order (please contact editors to suggest
corrections): Krste Asanovi´c, Rimas Aviˇzienis, Jacob Bachmeyer, Allen J. Baum, Paolo Bonzini,
Ruslan Bukin, Christopher Celio, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte Dal-
rymple, Dennis Ferguson, Mike Frysinger, John Hauser, David Horner, Olof Johansson, Yunsup
Lee, Andrew Lutomirski, Jonathan Neusch¨afer, Rishiyur Nikhil, Stefan O’Rear, Albert Ou, John
Ousterhout, David Patterson, Colin Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray
VanDeWalker, Megan Wachs, Andrew Waterman, and Reinoud Zandijk.
This document is released under a Creative Commons Attribution 4.0 International License.
This document is a derivative of the RISC-V privileged speciﬁcation version 1.9.1 released under
2010–2017 Andrew Waterman, Yunsup Lee, Rimas Aviˇzienis, David Patterson,
Krste Asanovi´c. Creative Commons Attribution 4.0 International License.
Please cite as: “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version
1.10”, Editors Andrew Waterman and Krste Asanovi´c, RISC-V Foundation, May 2017.
This is version 1.10 of the RISC-V privileged architecture proposal. Changes from version 1.9.1
• The previous version of this document was released under a Creative Commons Attribution
4.0 International Licence by the original authors, and this and future versions of this document
will be released under the same licence.
• The explicit convention on shadow CSR addresses has been removed to reclaim CSR space.
Shadow CSRs can still be added as needed.
• The mvendorid register now contains the JEDEC code of the core provider as opposed to
a code supplied by the Foundation. This avoids redundancy and oﬄoads work from the
• The interrupt-enable stack discipline has been simpliﬁed.
• An optional mechanism to change the base ISA used by supervisor and user modes has been
added to the mstatus CSR, and the ﬁeld previously called Base in misa has been renamed
to MXL for consistency.
• Clariﬁed expected use of XS to summarize additional extension state status ﬁelds in mstatus.
• Optional vectored interrupt support has been added to the mtvec and stvec CSRs.
• The SEIP and UEIP bits in the mip CSR have been redeﬁned to support software injection
of external interrupts.
• The mbadaddr register has been subsumed by a more general mtval register that can now
capture bad instruction bits on an illegal instruction fault to speed instruction emulation.
• The machine-mode base-and-bounds translation and protection schemes have been removed
from the speciﬁcation as part of moving the virtual memory conﬁguration to sptbr (now
satp). Some of the motivation for the base and bound schemes are now covered by the PMP
registers, but space remains available in mstatus to add these back at a later date if deemed
• In systems with only M-mode, or with both M-mode and U-mode but without U-mode
trap support, the medeleg and mideleg registers now do not exist, whereas previously they
• Virtual-memory page faults now have mcause values distinct from physical-memory access
exceptions. Page-fault exceptions can now be delegated to S-mode without delegating excep-
tions generated by PMA and PMP checks.
• An optional physical-memory protection (PMP) scheme has been proposed.
• The supervisor virtual memory conﬁguration has been moved from the mstatus register to
the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor
ii Volume II: RISC-V Privileged Architectures V1.10
Address Translation and Protection) to reﬂect is broadened role.
• The SFENCE.VM instruction has been removed in favor of the improved SFENCE.VMA
• The mstatus bit MXR has been exposed to S-mode via sstatus.
• The polarity of the PUM bit in sstatus has been inverted to shorten code sequences involving
MXR. The bit has been renamed to SUM.
• Hardware management of page-table entry Accessed and Dirty bits has been made optional;
simpler implementations may trap to software to set them.
• The counter-enable scheme has changed, so that S-mode can control availability of counters
• H-mode has been removed, as we are focusing on recursive virtualization support in S-mode.
The encoding space has been reserved and may be repurposed at a later date.
• A mechanism to improve virtualization performance by trapping S-mode virtual-memory
management operations has been added.
• The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained
as a separate speciﬁcation.
Volume II: RISC-V Privileged Architectures V1.10 iii
Preface to Version 1.9.1
This is version 1.9.1 of the RISC-V privileged architecture proposal. Changes from version 1.9
• Numerous additions and improvements to the commentary sections.
• Change conﬁguration string proposal to be use a search process that supports various formats
including Device Tree String and ﬂattened Device Tree.
• Made misa optionally writable to support modifying base and supported ISA extensions.
CSR address of misa changed.
• Added description of debug mode and debug CSRs.
• Added a hardware performance monitoring scheme. Simpliﬁed the handling of existing hard-
ware counters, removing privileged versions of the counters and the corresponding delta reg-
• Fixed description of SPIE in presence of user-level interrupts.
Use RISC-V to write a code: An array array1 contains the sequence -1 22 8 35 5 4 11 2 1 78, each element of which is .word. Rearrange the element order in this array such that, 1. All the elements smaller than the 3rd element (i.e. 8) are on the left of it, 2. All the elements bigger than the 3rd element (i.e. 8) are on the right of it.
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