SerialATA_SPEC_Revision_3_1_Gold.pdf

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Serial ATA Revision 3.1 – Gold Revision

Serial ATA International Organization:

Serial ATA Revision 3.1

18-July-2011

Gold Revision

SATA-IO Board Members:

Dell Computer Corporation

Hewlett Packard Corporation

Hitachi Global Storage Technologies, Inc.

Intel Corporation

Marvell Semiconductor

Maxim Integrated Products

Seagate Technology

Western Digital Corporation

FOR CSDN

HIGH SPEED SERIALIZED AT ATTACHMENT

Serial ATA International Organization

Serial ATA Revision 3.1 Gold Revision page 3 of 717

TABLE OF CONTENTS

1 Revision History .............................................................................................................. 21

1.1 Revision 2.5 (Ratification Date: October 27, 2005) ...................................................... 21

1.2 Revision 2.6 (Ratification Date: February 15, 2007) .................................................... 21

1.3 Revision 3.0 (Ratification Date: June 6, 2009) ............................................................. 21

1.4 Revision 3.1 (Ratification Date: July 18, 2011) ............................................................ 22

2 Scope .............................................................................................................................. 24

3 Normative references ..................................................................................................... 25

3.1 Approved references ..................................................................................................... 25

3.2 References under development .................................................................................... 27

3.3 Other references ............................................................................................................ 27

4 Definitions, abbreviations, and conventions ................................................................... 29

4.1 Terminology ................................................................................................................... 29

4.1.1 Definitions and abbreviations ................................................................................ 29

4.2 Conventions ................................................................................................................... 40

4.2.1 Precedence ............................................................................................................ 41

4.2.2 Keywords ............................................................................................................... 41

4.2.3 Numbering ............................................................................................................. 42

4.2.4 Dimensions ............................................................................................................ 42

4.2.5 Signal conventions ................................................................................................. 42

4.2.6 State machine conventions ................................................................................... 42

4.2.7 Byte, word and Dword Relationships ..................................................................... 43

5 General overview ............................................................................................................ 45

5.1 Architecture .................................................................................................................... 46

5.2 Usage Models ................................................................................................................ 47

5.2.1 Internal 1 meter Cabled Host to Device ................................................................. 50

5.2.2 Short Backplane to Device .................................................................................... 50

5.2.3 Long Backplane to Device (Obsolete) ................................................................... 51

5.2.4 Internal 4-lane Cabled Disk Arrays ........................................................................ 51

5.2.5 System-to-System Interconnects – Data Center Applications (xSATA) ................ 52

5.2.6 System-to-System Interconnects – External Desktop Applications (eSATA) ........ 54

5.2.7 Proprietary Serial ATA Disk Arrays ....................................................................... 55

5.2.8 Serial ATA and SAS .............................................................................................. 55

5.2.9 Potential External SATA Incompatibility Issues ..................................................... 56

5.2.10 Mobile Applications ................................................................................................ 56

5.2.11 SATA Universal Storage Module (SATA USM) ..................................................... 57

5.2.12 Port Multiplier Example Applications ..................................................................... 58

6 Cables and Connectors .................................................................................................. 63

6.1 Internal cables and connectors ...................................................................................... 63

6.1.1 Internal Single Lane Description ............................................................................ 63

6.1.2 Connector locations ............................................................................................... 66

6.1.3 Mating interfaces ................................................................................................... 75

6.1.4 Signal cable receptacle connector ......................................................................... 79

6.1.5 Signal host plug connector .................................................................................... 81

6.1.6 Backplane connector ............................................................................................. 83

6.1.7 Power cable receptacle connector ........................................................................ 87

6.1.8 Internal single lane cable material ......................................................................... 89

6.1.9 Connector labeling ................................................................................................. 90

6.1.10 Connector and cable assembly requirements and test procedures ...................... 90

6.1.11 Internal Multilane cables ........................................................................................ 94

6.1.12 Mini SATA Internal Multilane ............................................................................... 100

6.2 Internal Micro SATA Connector for 1.8” HDD ............................................................. 107

6.2.1 Usage model ........................................................................................................ 107

6.2.2 General description .............................................................................................. 107

Serial ATA Revision 3.1 Gold Revision page 4 of 717

6.2.3

 Connector location ............................................................................................... 107

6.2.4 Mating interfaces ................................................................................................. 110

6.3 Internal Slimline cables and connectors ...................................................................... 116

6.3.1 Usage Models ...................................................................................................... 116

6.3.2 General description .............................................................................................. 117

6.3.3 Connector location and keep out zones .............................................................. 118

6.3.4 Mating interfaces ................................................................................................. 122

6.3.5 Backplane connector configuration and blind-mating tolerance .......................... 134

6.3.6 Connector labeling ............................................................................................... 135

6.3.7 Connector and cable assembly requirements and test procedures .................... 135

6.4 Internal LIF-SATA Connector for 1.8” HDD ................................................................. 136

6.4.1 General description .............................................................................................. 136

6.4.2 Connector Locations ............................................................................................ 137

6.4.3 Mating interfaces ................................................................................................. 139

6.4.4 Internal LIF-SATA pin signal definition and contact mating sequence ................ 142

6.4.5 Housing and contact electrical requirement ........................................................ 144

6.5 mSATA Connector ....................................................................................................... 144

6.5.1 General description .............................................................................................. 144

6.5.2 Connector location on mSATA Host .................................................................... 144

6.5.3 Mating interfaces ................................................................................................. 147

6.5.4 mSATA pin signal definition ................................................................................. 150

6.6 SATA USM Connector Location .................................................................................. 153

6.6.1 USM Mating Interfaces ........................................................................................ 154

6.7 External cables and connectors .................................................................................. 158

6.7.1 External Single Lane ............................................................................................ 158

6.7.2 External Multilane ................................................................................................ 168

6.7.3 Mini SATA External Multilane .............................................................................. 172

6.8 Cable and Connector Electrical Specifications ............................................................ 176

6.8.1 Serial ATA Cable ................................................................................................. 176

6.8.2 Cable/Connector Test Methodology .................................................................... 177

6.9 Hardware Feature Control (Optional) .......................................................................... 183

6.9.1 Overview .............................................................................................................. 183

6.9.2 Electrical Requirements Specification ................................................................. 184

6.9.3 Device Activity Signal .......................................................................................... 185

6.9.4 Staggered Spin-up Disable Control ..................................................................... 187

6.9.5 Micro SATA Connector P7 Definition (optional) .................................................. 189

6.10 Precharge and Device Presence Detection ................................................................ 192

6.10.1 Device Requirements .......................................................................................... 192

6.10.2 Receptacle Precharge (Informative) .................................................................... 192

6.10.3 Presence Detection (Informative) ........................................................................ 194

7 Phy Layer ......................................................................................................................197

7.1 Descriptions of Phy Electrical Specifications ............................................................... 197

7.1.1 List of Services .................................................................................................... 198

7.1.2 Low Level Electronics Block Diagrams (Informative) .......................................... 198

7.1.3 Compliance Testing ............................................................................................. 205

7.1.4 Link Performance ................................................................................................. 206

7.2 Electrical Specifications ............................................................................................... 206

7.2.1 Physical Layer Requirements Tables .................................................................. 208

7.2.2 Phy Layer Requirements Details ......................................................................... 230

7.2.3 Loopback ............................................................................................................. 245

7.2.4 Test Pattern Requirements .................................................................................. 248

7.2.5 Hot Plug Considerations ...................................................................................... 272

7.2.6 Mated Connector Pair Definition .......................................................................... 274

7.2.7 Compliance Interconnect Channels (Gen3i, Gen3u) ........................................... 277

7.2.8 Impedance Calibration (Optional) ........................................................................ 279

7.3 Jitter ............................................................................................................................. 279

HIGH SPEED SERIALIZED AT ATTACHMENT

Serial ATA International Organization

Serial ATA Revision 3.1 Gold Revision page 5 of 717

7.3.1

 Jitter Definition ..................................................................................................... 280

7.3.2 Reference Clock Definition .................................................................................. 280

7.3.3 Spread Spectrum Clocking .................................................................................. 282

7.3.4 Jitter Budget ......................................................................................................... 284

7.4 Measurements ............................................................................................................. 285

7.4.1 Test fixtures ......................................................................................................... 285

7.4.2 Frame Error Rate Testing .................................................................................... 290

7.4.3 Measurement of Differential Voltage Amplitudes (Gen1, Gen2) ......................... 293

7.4.4 Measurement of Differential Voltage Amplitudes (Gen3i, Gen3u) ...................... 303

7.4.5 Rise and Fall Times ............................................................................................. 305

7.4.6 Transmitter Amplitude .......................................................................................... 306

7.4.7 Receive Amplitude ............................................................................................... 308

7.4.8 Long Term Frequency Accuracy ......................................................................... 310

7.4.9 Jitter Measurements ............................................................................................ 312

7.4.10 Transmit Jitter (Gen1i, Gen1m, Gen1u, Gen2i, Gen2m, Gen2u) ........................ 315

7.4.11 Transmit Jitter (Gen3i, Gen3u) ............................................................................ 316

7.4.12 Receiver Tolerance (Gen1i, Gen1m, Gen1u, Gen2i, Gen2m, Gen2u) ............... 318

7.4.13 Receiver Tolerance (Gen3i, Gen3u) .................................................................... 319

7.4.14 Return Loss and Impedance Balance ................................................................. 322

7.4.15 SSC Profile .......................................................................................................... 325

7.4.16 Intra-Pair Skew .................................................................................................... 326

7.4.17 Sequencing Transient Voltage ............................................................................ 328

7.4.18 AC Coupling Capacitor ........................................................................................ 329

7.4.19 TX Amplitude Imbalance ...................................................................................... 329

7.4.20 TX Rise/Fall Imbalance (Obsolete) ...................................................................... 329

7.4.21 TX AC Common Mode Voltage (Gen2i, Gen2m, Gen2u) ................................... 330

7.4.22 Tx AC Common Mode Voltage (Gen3i, Gen3u) .................................................. 330

7.4.23 OOB Common Mode Delta .................................................................................. 330

7.4.24 OOB Differential Delta ......................................................................................... 331

7.4.25 Squelch Detector Tests ....................................................................................... 331

7.4.26 OOB Signaling Tests ........................................................................................... 332

7.4.27 TDR Differential Impedance (Gen1i, Gen1m, Gen1u) ........................................ 333

7.4.28 TDR Single-Ended Impedance (Gen1i, Gen1m) ................................................. 334

7.4.29 DC Coupled Common Mode Voltage (Gen1i) ..................................................... 335

7.4.30 AC Coupled Common Mode Voltage (Gen1i, Gen1m) ....................................... 336

7.4.31 Sequencing Transient Voltage - Laboratory Load (Gen3i, Gen3u) ..................... 336

7.5 Interface States ............................................................................................................ 337

7.5.1 Out Of Band Signaling ......................................................................................... 337

7.5.2 Idle Bus Condition ................................................................................................ 345

7.6 Elasticity Buffer Management ...................................................................................... 345

8 OOB and Phy Power States .........................................................................................347

8.1 Interface Power States ................................................................................................ 347

8.2 Asynchronous Signal Recovery (Optional) .................................................................. 347

8.2.1 Unsolicited COMINIT Usage (Informative) .......................................................... 347

8.3 OOB and Signature FIS return (Informative) ............................................................... 348

8.4 Power-On Sequence State Machine ........................................................................... 348

8.4.1 Host Phy Initialization State Machine .................................................................. 348

8.4.2 Device Phy Initialization State Machine ............................................................... 353

8.4.3 Speed Negotiation ............................................................................................... 357

9 Link Layer .....................................................................................................................365

9.1 Overview ...................................................................................................................... 365

9.1.1 Frame Transmission ............................................................................................ 365

9.1.2 Frame Reception ................................................................................................. 365

9.2 Encoding Method ......................................................................................................... 365

9.2.1 Notation and Conventions ................................................................................... 366

9.2.2 Character Code ................................................................................................... 367

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