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SX1212 Transceiver
Ultra-Low Power Integrated 300-510MHz Transceiver
ADVANCED COMMUNICATIONS & SENSING
Rev 2 – June 18th, 2009 Page 1 of 77 www.semtech.com
General Description
The SX1212 is a low cost single-chip transceiver
operating in the frequency ranges from 300MHz to
510MHz. The SX1212 is optimized for very low power
consumption (3mA in receiver mode). It incorporates a
baseband modem with data rates up to 150 kb/s. Data
handling features include a sixty-four byte FIFO,
packet handling, automatic CRC generation and data
whitening. Its highly integrated architecture allows for
minimum external component count whilst maintaining
design flexibility. All major RF communication
parameters are programmable and most of them may
be dynamically set. It complies with European (ETSI
EN 300-220 V2.1.1) and North American (FCC part
15.247 and 15.249) regulatory standards.
Ordering Information
Table 1: Ordering Information
Part number Delivery
Minimum Order
Quantity / Multiple
SX1212IWLTRT Tape & Reel 3000 pieces
TQFN-32 package – Operating range [-40;+85°C]
T refers to Lead Free packaging
This device is WEEE and RoHS compliant
Features
Low Rx power consumption: 3mA
Low Tx power consumption: 25 mA @ +10 dBm
Good reception sensitivity: down to -104 dBm at
25 kb/s in FSK, -110 dBm at 2kb/s in OOK
Programmable RF output power: up to +12.5 dBm
in 8 steps
Packet handling feature with data whitening and
automatic CRC generation
RSSI (Received Signal Strength Indicator)
Bit rates up to 150 kb/s, NRZ coding
On-chip frequency synthesizer
FSK and OOK modulation
Incoming sync word recognition
Built-in Bit-Synchronizer for incoming data and
clock synchronization and recovery
5 x 5 mm TQFN package
Optimized Circuit Configuration for Low-cost
applications
Applications
Wireless alarm and security systems
Wireless sensor networks
Automated Meter Reading
Home and building automation
Industrial monitoring and control
Remote Wireless Control
Active RFID PHY
Application Circuit Schematic
SX1212
ADVANCED COMMUNICATIONS & SENSING
Rev 2 – June 18th, 2009
Page 2 of 77 www.semtech.com
Table of Contents
1. General Description ................................................................... 5
1.1. Simplified Block Diagram................................................... 5
1.2. Pin Diagram ....................................................................... 6
1.3. Pin Description................................................................... 7
2. Electrical Characteristics............................................................ 8
2.1. ESD Notice ........................................................................ 8
2.2. Absolute Maximum Ratings ............................................... 8
2.3. Operating Range ............................................................... 8
2.4. Chip Specification.............................................................. 8
2.4.1. Power Consumption .................................................. 8
2.4.2. Frequency Synthesis................................................. 9
2.4.3. Transmitter ................................................................ 9
2.4.4. Receiver .................................................................. 10
2.4.5. Digital Specification................................................. 11
3. Architecture Description........................................................... 12
3.1. Power Supply Strategy .................................................... 12
3.2. Frequency Synthesis Description .................................... 13
3.2.1. Reference Oscillator................................................ 13
3.2.2. CLKOUT Output ...................................................... 13
3.2.3. PLL Architecture...................................................... 14
3.2.4. PLL Tradeoffs.......................................................... 14
3.2.5. Voltage Controlled Oscillator................................... 15
3.2.6. PLL Loop Filter ........................................................ 16
3.2.7. PLL Lock Detection Indicator .................................. 16
3.2.8. Frequency Calculation ............................................ 16
3.3. Transmitter Description ................................................... 18
3.3.1. Architecture Description .......................................... 18
3.3.2. Bit Rate Setting ....................................................... 19
3.3.3. Alternative Settings ................................................. 19
3.3.4. Fdev Setting in FSK Mode ...................................... 19
3.3.5. Fdev Setting in OOK Mode ..................................... 19
3.3.6. Interpolation Filter ................................................... 20
3.3.7. Power Amplifier ....................................................... 20
3.3.8. Common Input and Output Front-End..................... 22
3.4. Receiver Description........................................................ 23
3.4.1. Architecture ............................................................. 23
3.4.2. LNA and First Mixer ................................................ 24
3.4.3. IF Gain and Second I/Q Mixer................................. 24
3.4.4. Channel Filters ........................................................ 24
3.4.5. Channel Filters Setting in FSK Mode ...................... 25
3.4.6. Channel Filters Setting in OOK Mode ..................... 26
3.4.7. RSSI ........................................................................ 26
3.4.8. Fdev Setting in Receive Mode ................................ 28
3.4.9. FSK Demodulator.................................................... 28
3.4.10. OOK Demodulator................................................. 28
3.4.11. Bit Synchronizer .................................................... 31
3.4.12. Alternative Settings ............................................... 32
3.4.13. Data Output ........................................................... 32
4. Operating Modes...................................................................... 33
4.1. Modes of Operation ......................................................... 33
4.2. Digital Pin Configuration vs. Chip Mode .......................... 33
5. Data Processing....................................................................... 34
5.1. Overview.......................................................................... 34
5.1.1. Block Diagram......................................................... 34
5.1.2. Data Operation Modes ............................................ 34
5.2. Control Block Description ................................................ 35
5.2.1. SPI Interface ........................................................... 35
5.2.2. FIFO ........................................................................ 38
5.2.3. Sync Word Recognition........................................... 39
5.2.4. Packet Handler........................................................ 40
5.2.5. Control......................................................................40
5.3. Continuous Mode .............................................................41
5.3.1. General Description .................................................41
5.3.2. Tx Processing ..........................................................41
5.3.3. Rx Processing ..........................................................42
5.3.4. Interrupt Signals Mapping ........................................42
5.3.5. uC Connections........................................................43
5.3.6. Continuous Mode Example ......................................43
5.4. Buffered Mode ..................................................................44
5.4.1. General Description .................................................44
5.4.2. Tx Processing ..........................................................44
5.4.3. Rx Processing ..........................................................45
5.4.4. Interrupt Signals Mapping ........................................46
5.4.5. uC Connections........................................................47
5.4.6. Buffered Mode Example...........................................47
5.5. Packet Mode.....................................................................49
5.5.1. General Description .................................................49
5.5.2. Packet Format..........................................................49
5.5.3. Tx Processing ..........................................................51
5.5.4. Rx Processing ..........................................................51
5.5.5. Packet Filtering ........................................................52
5.5.6. DC-Free Data Mechanisms......................................53
5.5.7. Interrupt Signal Mapping ..........................................54
5.5.8. uC Connections........................................................55
5.5.9. Packet Mode Example .............................................56
5.5.10. Additional Information ............................................56
6. Configuration and Status Registers ..........................................58
6.1. General Description..........................................................58
6.2. Main Configuration Register - MCParam..........................58
6.3. Interrupt Configuration Parameters - IRQParam ..............60
6.4. Receiver Configuration parameters - RXParam ...............62
6.5. Sync Word Parameters - SYNCParam.............................63
6.6. Transmitter Parameters - TXParam .................................64
6.7. Oscillator Parameters - OSCParam .................................64
6.8. Packet Handling Parameters – PKTParam ......................65
7. Application Information .............................................................66
7.1. Crystal Resonator Specification .......................................66
7.2. Software for Frequency Calculation .................................66
7.2.1. GUI...........................................................................66
7.2.2. .dll for Automatic Production Bench .........................66
7.3. Switching Times and Procedures .....................................66
7.3.1. Optimized Receive Cycle .........................................67
7.3.2. Optimized Transmit Cycle ........................................68
7.3.3. Transmitter Frequency Hop Optimized Cycle ..........69
7.3.4. Receiver Frequency Hop Optimized Cycle ..............70
7.3.5. RxÆTx and TxÆRx Jump Cycles............................71
7.4. Reset of the Chip..............................................................72
7.4.1. POR .........................................................................72
7.4.2. Manual Reset ...........................................................72
7.5. Reference Design.............................................................73
7.5.1. Application Schematic..............................................73
7.5.2. PCB Layout ..............................................................73
7.5.3. Bill Of Material..........................................................74
8. Packaging Information ..............................................................75
8.1. Package Outline Drawing .................................................75
8.2. PCB Land Pattern.............................................................75
8.3. Tape & Reel Specification ................................................76
9. Revision History ........................................................................77
10. Contact Information.................................................................77
SX1212
ADVANCED COMMUNICATIONS & SENSING
Rev 2 – June 18th, 2009
Page 3 of 77 www.semtech.com
Index of Figures
Figure 1: SX1212 Simplified Block Diagram .................................. 5
Figure 2: SX1212 Pin Diagram ...................................................... 6
Figure 3: SX1212 Detailed Block Diagram .................................. 12
Figure 4: Power Supply Breakdown............................................. 13
Figure 5: Frequency Synthesizer Description .............................. 14
Figure 6: LO Generator ................................................................ 14
Figure 7: Loop Filter ..................................................................... 16
Figure 8: Transmitter Architecture ............................................... 18
Figure 9: I(t), Q(t) Overview ......................................................... 18
Figure 10: PA Control................................................................... 21
Figure 11: Optimal Load Impedance Chart .................................. 21
Figure 12: Recommended PA Biasing and Output Matching ..... 22
Figure 13: Front-end Description ................................................. 22
Figure 14: Receiver Architecture ................................................. 23
Figure 15: FSK Receiver Setting ................................................. 23
Figure 16: OOK Receiver Setting ................................................ 23
Figure 17: Active Channel Filter Description................................ 24
Figure 18: Butterworth Filter's Actual BW .................................... 26
Figure 19: Polyphase Filter's Actual BW...................................... 26
Figure 20: RSSI Dynamic Range................................................. 27
Figure 21: RSSI IRQ Timings ...................................................... 28
Figure 22: OOK Demodulator Description ................................... 29
Figure 23: Floor Threshold Optimization...................................... 30
Figure 24: BitSync Description..................................................... 31
Figure 25: SX1212’s Data Processing Conceptual View ............. 34
Figure 26: SPI Interface Overview and uC Connections ............. 35
Figure 27: Write Register Sequence ............................................ 36
Figure 28: Read Register Sequence............................................ 37
Figure 29: Write Bytes Sequence (ex: 2 bytes) ........................... 37
Figure 30: Read Bytes Sequence (ex: 2 bytes) ........................... 38
Figure 31: FIFO and Shift Register (SR)...................................... 38
Figure 32: FIFO Threshold IRQ Source Behavior........................ 39
Figure 33: Sync Word Recognition ...............................................40
Figure 34: Continuous Mode Conceptual View.............................41
Figure 35: Tx Processing in Continuous Mode .............................41
Figure 36: Rx Processing in Continuous Mode.............................42
Figure 37: uC Connections in Continuous Mode ..........................43
Figure 38: Buffered Mode Conceptual View .................................44
Figure 39: Tx processing in Buffered Mode (FIFO size = 16,
Tx_start_irq_0=0) ...............................................................45
Figure 40: Rx Processing in Buffered Mode (FIFO size=16,
Fifo_fill_method=0).............................................................46
Figure 41: uC Connections in Buffered Mode...............................47
Figure 42: Packet Mode Conceptual View....................................49
Figure 43: Fixed Length Packet Format........................................50
Figure 44: Variable Length Packet Format ...................................51
Figure 45: CRC Implementation ...................................................53
Figure 46: Manchester Encoding/Decoding..................................54
Figure 47: Data Whitening ............................................................54
Figure 48: uC Connections in Packet Mode .................................55
Figure 49: Optimized Rx Cycle .....................................................67
Figure 50: Optimized Tx Cycle......................................................68
Figure 51: Tx Hop Cycle ...............................................................69
Figure 52: Rx Hop Cycle...............................................................70
Figure 53: Rx Æ Tx Æ Rx Cycle ...................................................71
Figure 54: POR Timing Diagram...................................................72
Figure 55: Manual Reset Timing Diagram ....................................72
Figure 56: Reference Design Circuit Schematic ...........................73
Figure 57: Reference Design‘s Stackup .......................................74
Figure 58: Reference Design Layout (top view)............................74
Figure 59: Package Outline Drawing ............................................75
Figure 60: PCB Land Pattern........................................................75
Figure 61: Tape & Reel Dimensions .............................................76
SX1212
ADVANCED COMMUNICATIONS & SENSING
Rev 2 – June 18th, 2009
Page 4 of 77 www.semtech.com
Index of Tables
Table 1: Ordering Information ........................................................ 1
Table 2: SX1212 Pinouts ............................................................... 7
Table 3: Absolute Maximum Ratings ............................................. 8
Table 4: Operating Range.............................................................. 8
Table 5: Power Consumption Specification ................................... 8
Table 6: Frequency Synthesizer Specification............................... 9
Table 7: Transmitter Specification ................................................. 9
Table 8: Receiver Specification.................................................... 10
Table 9: Digital Specification........................................................ 11
Table 10: MCParam_Freq_band Setting ..................................... 15
Table 11: PA Rise/Fall Times....................................................... 20
Table 12: Operating Modes ......................................................... 33
Table 13: Pin Configuration vs. Chip Mode ................................. 33
Table 14: Data Operation Mode Selection................................... 35
Table 15: Config vs. Data SPI Interface Selection....................... 36
Table 16: Status of FIFO when Switching Between Different
Modes of the Chip ............................................................. 39
Table 17: Interrupt Mapping in Continuous Rx Mode .................. 42
Table 18: Interrupt Mapping in Continuous Tx Mode................... 42
Table 19: Relevant Configuration Registers in Continuous Mode
(data processing related only)............................................43
Table 20: Interrupt Mapping in Buffered Rx and Stby Modes .......46
Table 21: Interrupt Mapping in Tx Buffered Mode ........................46
Table 22: Relevant Configuration Registers in Buffered Mode (data
processing related only) .....................................................47
Table 23: Interrupt Mapping in Rx and Stby in Packet Mode........55
Table 24: Interrupt Mapping in Tx Packet Mode ...........................55
Table 25: Relevant Configuration Registers in Packet Mode (data
processing related only) .....................................................56
Table 26: Registers List ................................................................58
Table 27: MCParam Register Description ....................................58
Table 28: IRQParam Register Description....................................60
Table 29: RXParam Register Description .....................................62
Table 30: SYNCParam Register Description ................................63
Table 31: TXParam Register Description .....................................64
Table 32: OSCParam Register Description ..................................64
Table 33: PKTParam Register Description ...................................65
Table 34: Crystal Resonator Specification....................................66
Table 35: Reference Design BOM ................................................74
Acronyms
BOM Bill Of Materials
BR Bit Rate
BW Bandwidth
CCITT
Comité Consultatif International
Téléphonique et Télégraphique - ITU
CP Charge Pump
CRC Cyclic Redundancy Check
DAC Digital to Analog Converter
DDS Direct Digital Synthesis
DLL Dynamically Linked Library
ERP
Equivalent Radiated Power
ETSI
European Telecommunications Standards
Institute
FCC Federal Communications Commission
Fdev Frequency Deviation
FIFO First In First Out
FS Frequency Synthesizer
FSK Frequency Shift Keying
GUI Graphical User Interface
IC Integrated Circuit
ID IDentificator
IF Intermediate Frequency
IRQ Interrupt ReQuest
ITU International Telecommunication Union
LFSR Linear Feedback Shift Register
LNA Low Noise Amplifier
LO Local Oscillator
LSB Least Significant Bit
MSB Most Significant Bit
NRZ Non Return to Zero
NZIF Near Zero Intermediate Frequency
OOK On Off Keying
PA Power Amplifier
PCB Printed Circuit Board
PFD Phase Frequency Detector
PLL Phase-Locked Loop
POR Power On Reset
RBW Resolution BandWidth
RF Radio Frequency
RSSI Received Signal Strength Indicator
Rx Receiver
SAW Surface Acoustic Wave
SPI Serial Peripheral Interface
SR Shift Register
Stby Standby
Tx Transmitter
uC Microcontroller
VCO Voltage Controlled Oscillator
XO Crystal Oscillator
XOR eXclusive OR
SX1212
ADVANCED COMMUNICATIONS & SENSING
Rev 2 – June 18th, 2009
Page 5 of 77 www.semtech.com
This product datasheet contains a detailed description of the SX1212 performance and functionality. Please consult
the Semtech website for the latest updates or errata.
1. General Description
The SX1212 is a single chip FSK and OOK transceiver capable of operation in the 300 to 510MHz license free ISM
frequency bands. It complies with both the relevant European and North American standards, EN 300-220 V2.1.1
(June 2006 release) and FCC Part 15 (10-1-2006 edition). A unique feature of this circuit is its extremely low
current consumption in receiver mode of only 3mA (typ).
The SX1212 comes in a 5x5 mm TQFN-32 package.
1.1. Simplified Block Diagram
Figure 1: SX1212 Simplified Block Diagram
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