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High Definition Audio Specification
Revision 1.0a
June 17, 2010
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Revision History
Revision
Purpose
Date
1.0
Initial Release
April 15, 2004
1.0a
Updated with DCN No: HDA001-A changes.
Updated with DCN No: HDA002-A changes.
Updated with DCN No: HDA006-A changes.
Updated with DCN No: HDA011-A changes.
Updated with DCN No: HDA012-A changes.
Updated with DCN No: HDA015-B changes.
Updated with DCN No: HDA016-A changes.
Updated with DCN No: HDA017-A changes.
Updated with DCN No: HDA019-A changes.
Updated with DCN No: HDA022-A changes.
Updated with DCN No: HDA024-A changes.
Updated with DCN No: HDA034-A2 changes.
Updated with DCN No: HDA035-A changes.
Updated with DCN No: HDA036-A changes.
Updated with DCN No: HDA039-A changes.
Updated with DCN No: HDA041-A changes.
Updated with DCN No: HDA042-A changes.
Errata:
Clarified Input Payload Capability and Output Payload
Capability Reset value is implementation specific.
Clarified that Stream Descriptor n FIFO Size must be valid
and static after every programming of data format register,
as well as when RUN bit is set.
Clarified that Stream Descriptor n BDL Pointer Upper Base
Address register attribute is RO if not supporting 64 bit
addressing.
Fixed timing error in “Codec Discovery” section that SW
should wait for at least 521 us (25 frames) after reading
CRST# as „1‟ before accessing codec.
Strongly recommend the default value for EAPD to be „1‟ in
“EAPD/BTL Enable” section.
Clarified the codec response expected for double Function
Group reset command in D3cold state, but recommended
no response for the first Function Group reset of the double
Function Group reset command sequence.
Clarified the reset value for FIFOS register is
implementation specific.
Clarified UR enable verb for function group node is
conditional in the required support for verbs table.
June 17, 2010
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Legal Notice
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS
FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF
ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including
liability for infringement of any proprietary rights, relating to use of information in this
specification. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein, except that a license is hereby granted to copy and reproduce this
specification for internal use only. Intel assumes no responsibility for any errors contained in this
document and has no liabilities or obligations for any damages arising from or in connection with
the use of this document.
Intel may make changes to specifications, product descriptions, and plans at any time, without
notice.
Intel may have patents or pending patent applications, trademarks, copyrights, or other intellectual
property rights that relate to the presented subject matter. The furnishing of documents and other
materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
*Other names and brands may be claimed as the property of others.
Copyright © 2003-2010, Intel Corporation. All rights reserved.
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Rev. 1.0a High Definition Audio Specification
iii
Contents
1 Introduction .................................................................................................. 16
1.1 Scope and Layout of This Document .......................................................................... 16
1.2 Motivation and Goals .................................................................................................. 16
1.2.1 AC„97 Compatibility ...................................................................................... 17
1.2.2 Feature List .................................................................................................. 17
1.2.3 Related Documents ...................................................................................... 17
2 Architecture Overview ................................................................................. 18
2.1 Hardware System Overview ....................................................................................... 18
2.2 Streams and Channels ............................................................................................... 19
2.3 DMA Channel Operation ............................................................................................ 21
2.4 Initialization and Enumeration ..................................................................................... 22
3 Register Interface ......................................................................................... 24
3.1 Introduction to Controller Registers ............................................................................ 24
3.1.1 Terminology ................................................................................................. 24
3.1.2 General Register Behaviors and Access Requirements ............................... 24
3.1.3 Behavior With 64-bit Addresses ................................................................... 25
3.2 High Definition Audio Controller System Bus Interface Registers ............................... 25
3.3 High Definition Audio Controller Register Set ............................................................. 25
3.3.1 Global Capabilities, Status, and Control ....................................................... 28
3.3.2 Offset 00h: GCAP – Global Capabilities ...................................................... 28
3.3.3 Offset 02h: VMIN – Minor Version ............................................................... 29
3.3.4 Offset 03h: VMAJ – Major Version ............................................................... 29
3.3.5 Offset 04h: OUTPAY – Output Payload Capability ...................................... 29
3.3.6 Offset 06h: INPAY – Input Payload Capability ............................................. 30
3.3.7 Offset 08h: GCTL – Global Control .............................................................. 30
3.3.8 Offset 0Ch: WAKEEN – Wake Enable ......................................................... 31
3.3.9 Offset 0Eh: STATESTS – State Change Status .......................................... 32
3.3.10 Offset 10h: GSTS – Global Status ............................................................... 32
3.3.11 Offset 18h: OUTSTRMPAY – Output Stream Payload Capability ................ 32
3.3.12 Offset 1Ah: INSTRMPAY – Input Stream Payload Capability ...................... 33
3.3.13 Interrupt Status and Control ......................................................................... 33
3.3.14 Offset 20h: INTCTL – Interrupt Control ........................................................ 34
3.3.15 Offset 24h: INTSTS – Interrupt Status .......................................................... 35
3.3.16 Offset 30h: Wall Clock Counter ................................................................... 35
3.3.17 Offset 38h: SSYNC – Stream Synchronization ............................................ 36
3.3.18 Offset 40h: CORB Lower Base Address ...................................................... 36
3.3.19 Offset 44h: CORBUBASE – CORB Upper Base Address ............................. 36
3.3.20 Offset 48h: CORBWP – CORB Write Pointer .............................................. 37
3.3.21 Offset 4Ah: CORBRP – CORB Read Pointer .............................................. 37
3.3.22 Offset 4Ch: CORBCTL – CORB Control ...................................................... 37
3.3.23 Offset 4Dh: CORBSTS – CORB Status ....................................................... 38
3.3.24 Offset 4Eh: CORBSIZE – CORB Size ......................................................... 38
3.3.25 Offset 50h: RIRBLBASE – RIRB Lower Base Address ................................ 39
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