ILI9806G驱动芯片技术规格说明书

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"ILI9806G数据手册是关于ILI9806G LCD显示器驱动芯片的详细技术文档，Version V100，发布日期为2014年4月17日。此芯片专为480(RGB)x864分辨率的a-SiTFT LCD屏幕设计，支持16.7M色彩，并内置GRAM。文档由台湾的ILITEK TECHNOLOGY CORP.发布。" ili9806g是一款单芯片驱动器，用于驱动a-SiTFT液晶显示屏，具有高分辨率和丰富的色彩表现力。这款芯片的主要特点包括： 1. **高分辨率**：480(RGB)x864的分辨率意味着它能够显示非常清晰、细腻的图像，适合于高画质的显示应用，如平板电脑、智能手机或高清显示屏。 2. **16.7M色彩**：内置的GRAM（图形随机存取内存）支持16.7百万色，提供宽广的色彩范围，确保了色彩的丰富性和图像的逼真度。 3. **系统接口**：芯片包含多种接口，如并行RGB接口，可以方便地与各种主控器进行连接，传输图像数据。 4. **地址计数器(AC)**：AC用于在显示过程中跟踪像素的位置，确保数据正确地写入到对应位置的GRAM中。 5. **灰度电压生成电路**：此电路负责根据数据信号生成相应的灰度等级电压，从而实现不同亮度级别的显示效果。 6. **时序生成**：时序生成部分负责产生驱动液晶面板所需的精确时序信号，包括帧率、行同步、列同步等，确保显示的同步性。 7. **振荡器**：提供稳定的时钟源，对整个显示系统的时序控制至关重要。 8. **源驱动电路**：源驱动电路负责将数据信号转换成驱动液晶单元的电压，控制每个像素的状态。 9. **面板控制电路**：这部分电路管理LCD面板的特定功能，如背光控制、对比度调节等。 10. **电源电路**：确保芯片和LCD面板获得稳定的工作电压，对显示质量和寿命有直接影响。 11. **MIPIDSI控制器**：MIPIDSI（Mobile Industry Processor Interface - Display Serial Interface）接口提供了高效的数据传输方式，适用于高速、低功耗的应用环境。 ILI9806G是一款集成了多种功能的高性能LCD驱动芯片，专为需要高质量、高分辨率显示的设备设计。其详细的技术规格和功能描述使得开发者能够充分利用其特性，实现优质、高效的显示效果。

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a-Si TFT LCD Single Chip Driver

480 (RGB) x 864 Resolution and 16.7M-color

ILI9806G

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.

Page 16 of 421

Figure 186: Noise on Power Supply Lines ............................................................................................................. 402

Figure 187: Spike/Glitch Rejection ......................................................................................................................... 403

Figure 188: Differential Inputs Logical 0 and 1, Threshold High/Low, Differential Voltage Range ......................... 405

Figure 189: Common Mode Voltage on Clock and Data Channels ........................................................................ 405

Figure 190: Differential Pair Termination Resistor on the Receiver Side ............................................................... 406

Figure 191: DSI Clock Channel Timing .................................................................................................................. 412

Figure 192: DSI Data to Clock Channel Timings .................................................................................................... 412

Figure 193: Rising and Falling Timings on Clock and Data Channels ................................................................... 413

Figure 194: BTA from the MPU to the Display Module ........................................................................................... 414

Figure 195: BTA from the Display Module to the MPU ........................................................................................... 414

Figure 196: Data Lanes - Low Power Mode to High Speed Mode Timings ............................................................ 415

Figure 197: Data Lanes - High Speed Mode to Low Power Mode Timings ............................................................ 416

Figure 198: Clock Lanes - High Speed Mode to/from Low Power Mode Timings .................................................. 417

Figure 199: Reference Circuit ................................................................................................................................. 419

a-Si TFT LCD Single Chip Driver

480 (RGB) x 864 Resolution and 16.7M-color

ILI9806G

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.

Page 17 of 421

List of Tables

Table 1: System Operating Mode ............................................................................................................................. 23

Table 2: Bus Interface Pins ....................................................................................................................................... 26

Table 3: Driver Output Pins ....................................................................................................................................... 29

Table 4: Charge Pump Relative Pins ........................................................................................................................ 30

Table 5: DC/DC Converter Pins ................................................................................................................................ 30

Table 6: Power Pins .................................................................................................................................................. 31

Table 7: Test Pins ...................................................................................................................................................... 32

Table 8: DBI Type B Parallel Interface ...................................................................................................................... 46

Table 9: DBI Type C Serial Interface ......................................................................................................................... 52

Table 10: DPI Interface Selection ............................................................................................................................. 61

Table 11: High Speed and Low-Power Lane Pair State Codes ................................................................................ 65

Table 12: Entering and Leaving Sequences ............................................................................................................. 71

Table 13: Escape Commands ................................................................................................................................... 72

Table 14: Abbreviations ............................................................................................................................................. 80

Table 15: Data Types (DT) from the MPU to the Display Module (ILI9806G) .......................................................... 89

Table 16: Data Types (DT) from the Display Module (ILI9806G) to the MPU .......................................................... 90

Table 17: One Bit Error Value of the Error Correction Code (ECC) .......................................................................... 97

Table 18: Display Command Set (DCS) Write, No Parameters (DCSWN-S) ......................................................... 101

Table 19: Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) .............................................................. 102

Table 20: Display Command Set (DCS) Write Long (DCSW-L) ............................................................................. 103

Table 21: Display Command Set (DCS) Read, No Parameter (DCSRN-S) ........................................................... 107

Table 22: Receiving and Transmitting EoTP during LPDT ..................................................................................... 111

Table 23: Acknowledge with Error Report (AwER) for Long Packet (LPa) Response ............................................ 115

Table 24: Acknowledge with Error Report (AwER) for Short Packet (SPa) Response ........................................... 115

Table 25: Interface Level Communication .............................................................................................................. 122

Table 26: Packet Level Communication ................................................................................................................. 122

Table 27: DCS Write, 1 Parameter Sequence – Example 1 ................................................................................... 123

Table 28: DCS Write, 1 Parameter Sequence – Example 2 ................................................................................... 123

Table 29: DCS Write, 1 Parameter Sequence – Example 3 ................................................................................... 123

Table 30: DCS Write, No Parameter Sequence – Example 1 ................................................................................ 124

Table 31: DCS Write, No Parameter Sequence – Example 2 ................................................................................ 124

Table 32: DCS Write, No Parameter Sequence – Example 3 ................................................................................ 124

Table 33: DCS Write Long Sequence – Example 1 ................................................................................................ 125

Table 34: DCS Write Long Sequence – Example 2 ................................................................................................ 125

Table 35: DCS Write Long Sequence – Example 3 ................................................................................................ 125

Table 36: DCS Write Long Sequence – Example 4 ................................................................................................ 127

Table 37: DCS Read, No Parameter Sequence – Example 1 ................................................................................ 127

a-Si TFT LCD Single Chip Driver

480 (RGB) x 864 Resolution and 16.7M-color

ILI9806G

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.

Page 18 of 421

Table 38: DCS Read, No Parameter Sequence – Example 2 ................................................................................ 128

Table 39: Null Packet, No Data Sequence - Example ............................................................................................ 129

Table 40: End of Transmission Packet – Example ................................................................................................. 129

Table 41: List of Supported MDDI Packets ............................................................................................................. 138

Table 42: Pixel Data Attributes ................................................................................................................................ 141

Table 43: 16/18-bit Color Data Mapping to 24-bit Pixel Data Operation ................................................................. 171

Table 44: Tearing Effect Line Timing ....................................................................................................................... 352

Table 45: Initial Values of Registers ........................................................................................................................ 376

Table 46: Output and I/O Pins ................................................................................................................................. 377

Table 47: Reset Timing ........................................................................................................................................... 378

Table 48: Reset Description .................................................................................................................................... 378

Table 49: Absolute Maximum Ratings .................................................................................................................... 400

Table 50: Spike/Glitch Rejection ............................................................................................................................. 403

Table 51: DSI Clock Channel Timing ...................................................................................................................... 412

Table 52: DSI Data to Clock Channel Timings ........................................................................................................ 412

Table 53: Rising and Falling Timings on Clock and Data Channels ....................................................................... 413

Table 54: Low Power State Period Timings – A ...................................................................................................... 414

Table 55: Low Power State Period Timings – B ...................................................................................................... 414

Table 56: Data Lanes - Low Power Mode to High Speed Mode Timings ............................................................... 415

Table 57: Data Lanes - High Speed Mode to Low Power Mode Timings ............................................................... 416

Table 58: Clock Lanes - High Speed Mode to/from Low Power Mode Timings ...................................................... 417

Table 59: External Component Table ...................................................................................................................... 420

a-Si TFT LCD Single Chip Driver

480 (RGB) x 864 Resolution and 16.7M-color

ILI9806G

The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.

Page 20 of 421

2. Features



Display resolution options:

 480 (RGB) (H) x 864 (V) with GRAM

 480 (RGB) (H) x 854 (V) with GRAM

 480 (RGB) (H) x 800 (V) with GRAM

 480 (RGB) (H) x 720 (V) with GRAM

 480 (RGB) (H) x 640 (V) with GRAM



Display color modes

 Full color mode:

16.7M colors (24-bit data, R: 8-bit, G: 8-bit, B: 8-bit)

 Reduced color modes:

262K colors (18-bit data, R: 6-bit, G: 6-bit, B: 6-bit)

65K colors (16-bit data, R: 5-bit, G: 6-bit, B: 5-bit)

8 colors (Idle Mode On): 8 colors (3-bit data, R: 1-bit, G: 1-bit, B: 1-bit)



Display module:

 On-chip Frame Memory size 1,244,160 bytes, 480 (RGB) (H) x 864 (V) x 24 bits

 Supports 1440 source channel outputs

 Supports gate control signals to gate driver in the panel

 Supports 1-dot/2-dot/3-dot/4-dot/column

 Gamma correction (1 preset Gamma curve)

 On module VCOM control (VCL+0.2V to 0V common electrode output voltage range)



Display interface types:

 MPU mode:

MIPI-DBI Type B (Display Bus Interface, 80 System) interface, 8/9/16/18/24-bit bus

MIPI-DBI Type C (Serial data transfer interface, 3-line SPI) interface

 MIPI-DSI (Display Serial Interface) interface:

Supports one data lane/maximum speed 850Mbps or

Supports two data lanes/maximum speed 500Mbps

Supports DSI version 1.01.00

Supports D-PHY version 1.00.00

Supports DCS version 1.02.00

 MDDI (Mobile Display Serial Interface):

Supports one data lane/maximum speed 800Mbps or

Supports two data lanes/maximum speed 400Mbps

Supports MDDI V1.2 1 strobe

 MIPI-DPI (Display Pixel Interface) interface:

16 bit/pixel (R: 5-bit, G: 6-bit, B: 5-bit)

18 bit/pixel (R: 6-bit, G: 6-bit, B: 6-bit)

24 bit/pixel (R: 8-bit, G: 8-bit, B: 8-bit)

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