ZedBoard Zynq-7000 ARM FPGA开发系统用户手册：全面功能与接口详解

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ZedBoard是一款基于Xilinx Zynq-7000系列的ARM+FPGA混合信号处理器平台，它旨在为用户提供一个高级别的、全面可编程逻辑与智能互联的开发系统。这款硬件用户手册版本1.1于2012年8月1日发布，提供了详细的系统介绍、功能描述以及各个模块的配置和使用指南。首先，ZedBoard的硬件设计包括了多种接口和功能组件，如： 1. **EPP（Enhanced Parallel Port）**：用于连接外部设备，提供标准并行数据传输接口。 2. **内存支持**：包括DDR3 SDRAM用于高速数据存储，以及SPI Flash作为非易失性存储器，用于程序和配置数据的存储。 3. **SD Card Interface**：允许通过SD卡进行文件传输和扩展存储空间。 4. **USB**：提供多种USB接口，如USB OTG（主机/设备模式）、USB-to-UART桥接用于串口通信，USB-JTAG用于调试，以及电路保护措施以确保安全。 5. **显示和音频接口**：包括HDMI输出用于高清视频，VGA接口，I2S音频编解码器用于音频处理，以及OLED显示器用于显示信息。 6. **时钟和复位源**：ZedBoard具有多种时钟源，如电源启动复位、程序按钮开关控制的复位，以及用于处理器子系统的内部复位。这些时钟和复位机制对于系统同步和初始化至关重要。 7. **用户输入/输出**：包含用户按钮、DIP开关和LED指示灯，便于用户交互和系统状态监控。 8. **以太网PHY**：提供10/100/1000 Mbps的网络连接，支持有线局域网应用。 9. **扩展接口**：包括LPCFMC连接器用于连接其他FPGA模块，以及Digilent Pmod兼容的接口，方便外设扩展。这份用户手册详述了如何配置和操作这些功能，从基础设置到高级特性，适合深入理解Zynq-7000平台的开发者使用。通过阅读和实践手册中的内容，用户可以充分利用ZedBoard进行嵌入式系统设计，开发出高性能、灵活的解决方案。

1-Aug-2012

2 Functional Description

2.1 EPP

The ZedBoard features a Xilinx Zynq XC7Z020-1CSG484 EPP. The initial ZedBoards ship with

Engineering Sample "CES" grade silicon. Later shipments will eventually switch to production "C"

grade silicon once they become available. The EPP part markings indicate the silicon grade.

2.2 Memory

Zynq contains a hardened PS memory interface unit. The memory interface unit includes a

dynamic memory controller and static memory interface modules.

2.2.1 DDR3

The ZedBoard includes two Micron MT41K128M16HA-15E:D DDR3 memory components

creating a 32-bit interface. The DDR3 is connected to the hard memory controller in the

Processor Subsystem (PS) as outlined in the Zynq datasheet.

The multi-protocol DDR memory controller is configured for 32-bit wide accesses to a 512 MB

address space. The PS incorporates both the DDR controller and the associated PHY, including

its own set of dedicated I/Os. DDR3 memory interface speeds up to 533MHz (1066Mbs) are

supported.

The DDR3 uses 1.5V SSTL-compatible inputs. DDR3 Termination is utilized on the ZedBoard.

The EPP and DDR3 have been placed close together keeping traces short and matched.

DDR3 on the PS was routed with 40 ohm trace impedance for single-ended signals, and DCI

resistors (VRP/VRN) as well as differential clocks set to 80 ohms. Each DDR3 chip needs its

own 240-ohm pull-down on ZQ.

DDR-VDDQ is set to 1.5V to support the DDR3 devices selected. DDR-VTT is the termination

voltage which is ½ DDR-VDDQ. DDR-VREF is a separate buffered output that is equal to ½

nominal DDR-VDDQ. The DDR-VREF is isolated to provide a cleaner reference for the DDR

level transitions.

1-Aug-2012

The PCB design guidelines outlined in Zynq datasheet must be followed for trace matching, etc.

Table 1 - DDR3 Connections

Signal Name

Description

Zynq EPP pin

DDR3 pin

DDR_CK_P

Differential clock

output

DDR_CK_N

Differential clock

output

DDR_CKE

Clock enable

DDR_CS_B

Chip select

DDR_RAS_B

RAS row address

select

DDR_CAS_B

RAS column address

select

DDR_WE_B

Write enable

DDR_BA[2:0]

Bank address

PS_DDR_BA[2:0]

BA[2:0]

DDR_A[14:0]

Address

PS_DDR_A[14:0]

A[14:0]

DDR_ODT

Output dynamic

termination

DDR_RESET_B

Reset

DDR_DQ[31:0]

I/O Data

PS_DDR_[31:0]

DDR3_DQ pins

DDR_DM[3:0]

Data mask

PS_DDR_DM[3:0]

LDM/UDM x2

DDR_DQS_P[3:0]

I/O Differential data

strobe

PS_DDR_DQS_P[3:0]

UDQS/LDQS

DDR_DQS_N[3:0]

I/O Differential data

strobe

PS_DDR_DQS_N[3:0]

UDQS#/LDQS#

DDR_VRP

I/O Used to calibrate

input termination

N/A

DDR_VRN

I/O Used to calibrate

input termination

N/A

DDR_VREF[1:0]

I/O Reference

voltage

H7, P7

For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read

data eye options in the PS Configuration Tool in Xilinx Platform Studio (XPS). The PS

Configuration tools’ Memory Configuration Wizard contains two entries to allow for DQS to Clock

Delay and Board Delay information to be specified for each of the four byte lanes. These

parameters are specific to every PCB design. Xilinx Answer Record 46778 provides a tool for

calculating these parameters by a printed circuit board design engineers. The Excel worksheet

file ar46778_board_delay_calc.xlsx included in the answer record provides instructions in the

worksheet for calculating these board training details based upon specific trace lengths for certain

DDR3 signals. Using the information from the trace length reports pertaining to the DDR3

interface for ZedBoard these delay values can be recreated by following the directions found in

the Excel worksheet.

The PCB lengths are contained in the ZedBoard PCB trace length reports. The DQS to CLK

Delay and Board Delay values are calculated specific to the ZedBoard memory interface PCB

design. The AR46778 worksheet allows for up to 4 memory devices to be configured for DDR3

4x8 flyby topology. Note that ZedBoard is configured for DDR3 2x16 flyby routing topology. The

first two clock trace midpoint values (CLK0 and CLK1) are used to represent the Micron device

electrically nearest to 7Z020 (IC26) and the second two clock trace midpoint values (CLK2 and

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