RK3288 TRM
FuZhou Rockchip Electronics Co.,Ltd. 1551
Chapter 45 SAR-ADC
45.1 Overview
The ADC is a 3-channel signal-ended 10-bit Successive Approximation Register (SAR) A/D
Converter. It uses the supply and ground as it reference which avoid use of any external
reference. It converts the analog input signal into 10-bit binary digital codes at maximum
conversion rate of 100KSPS with 1MHz A/D converter clock.
45.2 Block Diagram
SARADC_AIN[2:0]
REFP (VDDA_SARADC)
Fig. 45-1 RK3288 SAR-ADC block diagram
Successive-Approximate Register and Control Logic Block
This block is exploited to realize binary search algorithm, storing the intermediate result and
generate control signal for analog block.
Comparator Block
This block compares the analog input SARADC_AIN[2:0] with the voltage generated from D/A
Converter, and output the comparison result to SAR and Control Logic Block for binary search.
Three level amplifiers are employed in this comparator to provide enough gain.
45.3 Function description
In RK3288, SAR-ADC works at single-sample operation mode.
This mode is useful to sample an analog input when there is a gap between two samples to be
converted. In this mode START is asserted only on the rising edge of CLKIN where conversion
is needed. At the end of every conversion EOC signal is made high and valid output data is
available at the rising edge of EOC.The detailed timing diagram will be shown in the following.
45.4 Register Description
This section describes the control/status registers of the design.
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