8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Cyclone V GX SoC Bank 3 & 4
PCIE INTERFACE
HSMC LVCMOS INTERFACE
2.5 Volt
1.5 Volt
1.5 Volt
LVCMOS Only
DDR3_FPGA_CLK_P
DDR3_FPGA_CASn
DDR3_FPGA_RASn
DDR3_FPGA_WEn
DDR3_FPGA_CSn
DDR3_FPGA_BA2
DDR3_FPGA_BA1
DDR3_FPGA_BA0
DDR3_FPGA_CLK_N
DDR3_FPGA_A7
DDR3_FPGA_A8
DDR3_FPGA_A13
DDR3_FPGA_A6
DDR3_FPGA_A12
DDR3_FPGA_A9
DDR3_FPGA_A14 DDR3_FPGA_A4
DDR3_FPGA_A10
DDR3_FPGA_A5
DDR3_FPGA_A11
DDR3_FPGA_A1
DDR3_FPGA_A0
DDR3_FPGA_DM1
DDR3_FPGA_DM0
DDR3_FPGA_ODT
DDR3_FPGA_RESETn
DDR3_FPGA_CKE
DDR3_FPGA_DM2
DDR3_FPGA_DM3
DDR3_FPGA_DQ7
DDR3_FPGA_DQ0
DDR3_FPGA_DQS_P0
DDR3_FPGA_DQ13
DDR3_FPGA_DQ14
DDR3_FPGA_DQ8
DDR3_FPGA_DQ2
DDR3_FPGA_DQS_P1
DDR3_FPGA_DQS_N1
DDR3_FPGA_DQS_N0
DDR3_FPGA_DQ10
DDR3_FPGA_DQ4
DDR3_FPGA_DQ15
DDR3_FPGA_DQ9
DDR3_FPGA_DQ3
DDR3_FPGA_DQ1
DDR3_FPGA_DQ12
DDR3_FPGA_DQ6
DDR3_FPGA_DQ11
DDR3_FPGA_DQ5
DDR3_FPGA_DQ23
DDR3_FPGA_DQ16
DDR3_FPGA_DQS_P2
DDR3_FPGA_DQ29
DDR3_FPGA_DQ30
DDR3_FPGA_DQ24
DDR3_FPGA_DQ18
DDR3_FPGA_DQS_P3
DDR3_FPGA_DQS_N3
DDR3_FPGA_DQS_N2
DDR3_FPGA_DQ26
DDR3_FPGA_DQ20
DDR3_FPGA_DQ31
DDR3_FPGA_DQ25
DDR3_FPGA_DQ19
DDR3_FPGA_DQ17
DDR3_FPGA_DQ28
DDR3_FPGA_DQ22
DDR3_FPGA_DQ27
DDR3_FPGA_DQ21
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
HSMA_SDA
HSMA_SCL
USER_DIPSW_FPGA1
USER_DIPSW_FPGA3
USER_DIPSW_FPGA0
USER_DIPSW_FPGA2
USER_PB_FPGA0
USER_PB_FPGA1
USB_B2_DATA[7:0]
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_B2_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
DDR3_FPGA_DM3
DDR3_FPGA_DM2
DDR3_FPGA_CLK_P
DDR3_FPGA_CASn
DDR3_FPGA_RASn
DDR3_FPGA_WEn
DDR3_FPGA_CSn
DDR3_FPGA_BA2
DDR3_FPGA_ODT
DDR3_FPGA_RESETn
DDR3_FPGA_BA1
DDR3_FPGA_CKE
DDR3_FPGA_BA0
DDR3_FPGA_CLK_N
DDR3_FPGA_DM0
DDR3_FPGA_DM1
HSMA_PRSNTn
USB_B2_DATA0
USB_B2_DATA1
USB_B2_DATA2
USB_B2_DATA3
USB_B2_DATA4
USB_B2_DATA5
USB_B2_DATA6
USB_B2_DATA7
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_B2_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
RZQIN_1_5V
USER_LED_FPGA0
PCIE_PERSTn
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_SDA
17
HSMA_SCL
17
HSMA_D[3:0]
17
ENET2_RX_D[3..0]
5,19
ENET2_TX_D[3..0]
5,19
HSMA_PRSNTn
16,17,23
USB_B2_DATA[7:0]25
USB_FULL25
USB_EMPTY25
USB_SDA25
USB_RESETn25
USB_OEn25
USB_RDn25
USB_WRn25
USB_SCL25
USB_B2_CLK16,25
DDR3_FPGA_DM[3:0]
13
DDR3_FPGA_BA[2:0]
13
DDR3_FPGA_DQS_P[3:0]
13
DDR3_FPGA_DQS_N[3:0]
13
DDR3_FPGA_A[14:0]
9,13
DDR3_FPGA_DQ[31:0]
13
DDR3_FPGA_CKE
13
DDR3_FPGA_CLK_P
13
DDR3_FPGA_CLK_N
13
DDR3_FPGA_DM2
13
DDR3_FPGA_DM3
13
DDR3_FPGA_CSn
13
DDR3_FPGA_WEn
13
DDR3_FPGA_RASn
13
DDR3_FPGA_CASn
13
DDR3_FPGA_BA0
13
DDR3_FPGA_BA1
13
DDR3_FPGA_BA2
13
DDR3_FPGA_RESETn
13
DDR3_FPGA_ODT
13
DDR3_FPGA_DM1
13
DDR3_FPGA_DM0
13
USER_DIPSW_FPGA[3:0]
23
USER_PB_FPGA[1:0]
23
SDI_CLK148_UP
8
SDI_CLK148_DN
8
USER_LED_FPGA[3:0]
9,23
P1TXERR
19
P0TXERR
19
ENET_DUAL_RESETn
19,21
PCIE_PERSTn
3,11
HSMA_CLK_OUT_P1
17
HSMA_CLK_OUT_N1
17
HSMA_CLK_IN_P1
17
HSMA_CLK_IN_N1
17
Title
Size Document Number Rev
Date: Sheet of
C
Cyclone V SoC FPGA Development Kit Board
B
4 40Wednesday, March 20, 2013
150-0321003-C1 (6XX-44184R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C
Cyclone V SoC FPGA Development Kit Board
B
4 40Wednesday, March 20, 2013
150-0321003-C1 (6XX-44184R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
C
Cyclone V SoC FPGA Development Kit Board
B
4 40Wednesday, March 20, 2013
150-0321003-C1 (6XX-44184R)
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Bank 3A
Bank 3B
CYCLONE V GX SoC BANK 3
5CSXFC6D_F896
U21A
DIFFIO_TX_B12p
AF6
DIFFIO_RX_B14n,DQ2B
AJ2
DIFFIO_TX_B29n,DQ4B,B_A_11
AK9
DIFFIO_TX_B33n,GND
AJ10
DIFFIO_RX_B34p,DQ5B,B_BA_1
AJ11
DIFFIO_TX_B33p,DQ5B,B_BA_0
AH10
DIFFIO_TX_B36n,DQ5B,B_A_7
AK13
DIFFIO_RX_B35n,DQSn5B,B_CK#
AA15
DIFFIO_TX_B36p,B_A_6
AK12
DIFFIO_RX_B35p,DQS5B,B_CK
AA14
DIFFIO_RX_B38p,DQ5B,B_A_4
AG15
DIFFIO_RX_B38n,DQ5B,B_A_5
AH15
DIFFIO_TX_B40p,DQ5B,B_A_0
AJ14
DIFFIO_TX_B40n,DQ5B,B_A_1
AK14
DIFFIO_TX_B13n,DQ2B
AH5
DIFFIO_RX_B14p,DQ2B
AJ1
DIFFIO_TX_B13p,DQ2B
AG5
DIFFIO_TX_B16n,DQ2B
AH3
DIFFIO_RX_B15n
AD12
DIFFIO_TX_B16p,DQ2B
AG2
DIFFIO_RX_B15p
AC12
DIFFIO_TX_B28n,DQ4B,B_A_13
AK8
DIFFIO_RX_B27n,DQSn4B,B_CS#_1
AC14
DIFFIO_TX_B28p,B_A_12
AK7
DIFFIO_RX_B27p,DQS4B,B_CS#_0
AB15
DIFFIO_RX_B30n,DQ4B,B_A_9
AH14
DIFFIO_RX_B19n,DQSn3B
AB13
DIFFIO_RX_B11n,DQSn2B
AB12
DIFFIO_RX_B18n,DQ3B
AG11
DIFFIO_RX_B10n,DQ2B
AH2
DIFFIO_TX_B12n,DQ2B
AG6
DIFFIO_RX_B26n,DQ4B,B_A_15
AG13
DIFFIO_TX_B21n,DQ3B
AK4
DIFFIO_TX_B24n,DQ3B
AK6
DIFFIO_RX_B19p,DQS3B
AA13
DIFFIO_RX_B26p,DQ4B,B_A_14
AG12
DIFFIO_RX_B22p,DQ3B
AE13
DIFFIO_TX_B9n
AG7
DIFFIO_RX_B22n,DQ3B
AF13
DIFFIO_RX_B11p,DQS2B
AA12
DIFFIO_TX_B17n
AH9
DIFFIO_TX_B24p,DQ3B
AJ5
DIFFIO_TX_B20n,DQ3B
AK3
DIFFIO_TX_B20p
AK2
DIFFIO_TX_B25p,DQ4B,B_WE#
AJ6
DIFFIO_TX_B21p,DQ3B
AJ4
DIFFIO_TX_B17p,DQ3B
AG10
DIFFIO_TX_B25n,GND
AJ7
DIFFIO_RX_B18p,DQ3B
AF11
DIFFIO_TX_B8p,DQ1B
AF9
DIFFIO_RX_B10p,DQ2B
AG1
DIFFIO_RX_B23n
AE14
DIFFIO_TX_B9p,DQ2B
AF8
DIFFIO_RX_B23p
AD14
DIFFIO_RX_B30p,DQ4B,B_A_8
AH13
DIFFIO_TX_B29p,DQ4B,B_A_10
AJ9
DIFFIO_TX_B32n,DQ4B,B_RAS#
AH8
DIFFIO_TX_B32p,DQ4B,B_CAS#
AH7
DIFFIO_RX_B34n,DQ5B,B_BA_2
AK11
R449
100, 1%
Bank 4A
CYCLONE V GX SoC BANK 4
5CSXFC6D_F896
U21B
DIFFIO_TX_B61n,DQ8B,GND
AJ22
DIFFIO_RX_B42n,DQ6B,B_DQ_0
AF18
DIFFIO_RX_B62n,DQ8B,B_DQ_20
AF21
RZQ_0,DIFFIO_TX_B41n
AG17
DIFFIO_RX_B42p,DQ6B,B_DQ_1
AE17
DIFFIO_RX_B62p,DQ8B,B_DQ_21
AF20
DIFFIO_TX_B41p,DQ6B,B_DQ_2
AG16
DIFFIO_TX_B61p,DQ8B,B_DQ_22
AH23
DIFFIO_TX_B64n,DQ8B,B_DQ_23
AK24
DIFFIO_TX_B44n,DQ6B,B_DQ_3
AF16
DIFFIO_RX_B63n,GND
AA19
DIFFIO_RX_B43n,DQSn6B,B_DQS#_0
W16
DIFFIO_TX_B64p,DQ8B,B_DM_2
AK23
DIFFIO_RX_B63p,GND
Y18
DIFFIO_RX_B66n,DQ9B,B_DQ_24
AF24
DIFFIO_TX_B44p,B_ODT_0
AE16
DIFFIO_TX_B65n,GND
AJ25
DIFFIO_RX_B43p,DQS6B,B_DQS_0
V16
DIFFIO_RX_B46n,DQ6B,B_DQ_4
AH20
DIFFIO_RX_B66p,DQ9B,B_DQ_25
AF23
DIFFIO_TX_B45n,DQ6B,B_ODT_1
AK16
DIFFIO_TX_B65p,DQ9B,B_DQ_26
AJ24
DIFFIO_TX_B68n,DQ9B,B_DQ_27
AK26
DIFFIO_RX_B46p,DQ6B,B_DQ_5
AG21
DIFFIO_RX_B67n,DQSn9B,B_DQS#_3
AD19
DIFFIO_TX_B45p,DQ6B,B_DQ_6
AJ16
DIFFIO_TX_B68p,GND
AJ26
DIFFIO_RX_B67p,DQS9B,B_DQS_3
AC20
DIFFIO_RX_B70n,DQ9B,B_DQ_28
AE23
DIFFIO_TX_B48p,DQ6B,B_DM_0
AH17
DIFFIO_TX_B69n,DQ9B,GND
AH25
DIFFIO_TX_B48n,DQ6B,B_DQ_7
AH18
DIFFIO_RX_B50n,DQ7B,B_DQ_8
AK18
DIFFIO_RX_B70p,DQ9B,B_DQ_29
AE22
DIFFIO_TX_B69p,DQ9B,B_DQ_30
AG25
DIFFIO_TX_B72n,DQ9B,B_DQ_31
AK27
DIFFIO_RX_B71n,GND
W19
DIFFIO_TX_B72p,DQ9B,B_DM_3
AJ27
DIFFIO_RX_B71p,GND
V18
DIFFIO_RX_B74n,DQ10B,B_DQ_32
AD21
DIFFIO_TX_B73n,GND
AK29
DIFFIO_RX_B74p,DQ10B,B_DQ_33
AD20
DIFFIO_TX_B73p,DQ10B,B_DQ_34
AK28
DIFFIO_TX_B76n,DQ10B,B_DQ_35
AH27
DIFFIO_RX_B75n,DQSn10B,B_DQS#_4
AA20
DIFFIO_TX_B76p,GND
AG26
DIFFIO_RX_B75p,DQS10B,B_DQS_4
Y19
DIFFIO_RX_B78n,DQ10B,B_DQ_36
AC23
DIFFIO_TX_B77n,DQ10B,GND
AF26
DIFFIO_RX_B78p,DQ10B,B_DQ_37
AC22
DIFFIO_TX_B77p,DQ10B,B_DQ_38
AF25
DIFFIO_TX_B80n,DQ10B,B_DQ_39
AE24
DIFFIO_RX_B79n,GND
AB21
DIFFIO_TX_B80p,DQ10B,B_DM_4
AD24
DIFFIO_RX_B79p,GND
AA21
DIFFIO_TX_B60p,B_RESET#
AK21
DIFFIO_RX_B59n,DQSn8B,B_DQS#_2
AA18
DIFFIO_RX_B58n,DQ8B,B_DQ_16
AE19
DIFFIO_TX_B57n,GND
AH22
DIFFIO_TX_B52p,B_CKE_1
AJ19
DIFFIO_TX_B56p,DQ7B,B_DM_1
AG23
DIFFIO_RX_B54p,DQ7B,B_DQ_13
AF19
DIFFIO_RX_B58p,DQ8B,B_DQ_17
AE18
DIFFIO_TX_B53n,DQ7B,B_CKE_0
AJ21
DIFFIO_TX_B52n,DQ7B,B_DQ_11
AK19
DIFFIO_RX_B51p,DQS7B,B_DQS_1
V17
DIFFIO_TX_B57p,DQ8B,B_DQ_18
AG22
DIFFIO_TX_B53p,DQ7B,B_DQ_14
AJ20
DIFFIO_TX_B56n,DQ7B,B_DQ_15
AH24
DIFFIO_RX_B59p,DQS8B,B_DQS_2
Y17
DIFFIO_RX_B50p,DQ7B,B_DQ_9
AJ17
DIFFIO_TX_B60n,DQ8B,B_DQ_19
AK22
DIFFIO_TX_B49p,DQ7B,B_DQ_10
AG18
DIFFIO_RX_B51n,DQSn7B,B_DQS#_1
W17
DIFFIO_TX_B49n,GND
AH19
DIFFIO_RX_B54n,DQ7B,B_DQ_12
AG20
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