A3P1000FPGA说明_A3P1000

需积分: 50 188 浏览量更新于2023-06-09 评论 1 收藏 1.58MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

August 2012 1

Migrating Designs in ProASIC3 Devices from

Higher-Density to Mid-Density Devices

Introduction

The purpose of this document is to assist in migrating designs in ProASIC

3 A3P1000, A3P600, and

A3P400 devices from higher-density to mid-density devices. There are three possible migration paths:

• A3P1000 to A3P600

• A3P1000 to A3P400

• A3P600 to A3P400

Since one of the key factors is pin compatibility, this document addresses pin compatibility for all

available packages common to the A3P1000, A3P600, and A3P400 devices.

Design Migration

ProASIC3 family devices are architecturally compatible with each other. However, designers must pay

attention to a few key areas when migrating a design. The specific issues discussed throughout this

application note are as follows:

• "Design and Device Evaluation"

• "Device and Package Compatibility" on page 2

• "Migration and Implementation Methodologies" on page 3

• "I/O Banks and Standards" on page 4

• "Power Supply and Board-Level Considerations" on page 4

• "Pin Migration and Compatibility" on page 5

Design and Device Evaluation

When migrating a design, the primary task should be to compare the available resources between the

two devices. The designer should evaluate effective gate count, RAM size, I/O banks, and number of

I/Os (Table 1). In addition, necessary design timing analysis and simulations should be validated when

porting designs to new ProASIC3 derivatives.

Table 1 • Device Information

A3P1000 A3P600 A3P400

System Gates 1 M 600 k 400 k

Tiles (D-flip-flop) 24,576 13,824 9,126

RAM (kbits) 144 108 54

RAM Blocks (4,608 bits) 32 24 12

I/O Banks (+ JTAG) 444

Maximum User I/Os per Package

PQ208

FG144

FG256

FG484

154/35

97/25

177/44

300/74

154/35

97/25

177/43

235/60

151/34

97/25

178/38

194/38

Note: Maximum user I/O is listed as single-ended/double-ended.

Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices

August 2012 3

Migration and Implementation Methodologies

Table 3 lists some possible migration combinations and the recommended implementation rules for

compatible design conversions from higher-density to lower-density devices. The "Pin Migration and

Compatibility" section on page 5 contains tables that list the required rules for different pin combinations.

If “Rule x” is mentioned for a pin combination, that combination requires the implementation methodology

given in Table 3. Note that many combinations of high-density/low-density pins do not require these

rules; the pins have complete type compatibility. These pins are marked in the pin tables with “None.”

Table 3 • Migration Rules from Higher-Density to Mid-Density Devices

Migration

Rule

Issue

Implementation MethodologyHigher Density Lower Density

1 I/O or global I/O NC Leave this pin floating OR program I/Os as unused (software

cannot program NC to usable I/O).

2 Single-ended I/O Global I/O Instantiate the I/O buffer as a global single-ended I/O.

3 Global I/O Single-ended I/O Use the physical design constraint (PDC) to promote the

single-ended I/O to a global pin. There is an additional delay

that affects the setup time on the board. Or, do not use this

pin as a global input on the higher-density device.

4 VCC or VCCIB(x)

1,3

NC Leave pin connected to board VCC or VCCIBx plane.

5 VCCIB(x)

VCCIB(y)

Make sure the two bank voltage levels are the same. Tie the

pin to the board’s corresponding VCCIBx/VMVx plane.

6 VMV(x)

VMV(y)

Make sure the two bank voltage levels are the same. Tie pin

to the board’s corresponding VCCIBx/VMVx plane.

7 VMV(x)

I/O or global I/O Leave the pin tied to the board VCCIBx/VMVx plane.

Instantiate the I/Os as tristate buffers with OE = 0 and no

weak pull-ups/-downs.

8 GNDQ Global I/O Leave both pins tied to board GNDQ plane. Instantiate the

I/O as tristate buffer with OE = 0 and no weak pull-ups/-

downs.

9 GNDQ NC GNDQ and NC need to be connected to GND.

10 NC VCC or VCCIB(x)

1,3

Leave pin connected to board VCC or VCCIBx plane.

Notes:

1. (x) = 1, 2, 3, or 4

2. (y) = 1, 2, 3, or 4

3. Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter of the IGLOO FPGA Fabric User’s Guide

or ProASIC3 FPGA Fabric User’s Guide for I/O naming conventions.

剩余40页未读，继续阅读

35617547

粉丝: 0
资源: 1

会员权益专享

A3P1000 FPGA 说明

评论0

会员权益专享

最新资源

A3P1000 FPGA 说明

评论0

FPGA ACTEL A3P030中

ACTEL的FPGA开发资料

FPGA_A3P系列数据书册.pdf

a3p1000反熔丝

洛谷P1000怎么做？

p1000超级玛丽游戏

P1000 超级玛丽游戏

洛谷p1000超级玛丽游戏

p1000python超级玛丽

写洛谷P1000的代码

基于32单片机写一段机采集温度信号，热敏电阻P1000,放大器为ina350芯片的代码

用g代码写一个控制步进电机在限位a，b间移动，每次走1000步 循环80次，每次间隔一秒

cuda 11.1的gpu列表

python写nc文件

上位机用python写一个控制5轴机械臂到指定角度运动的代码

尼康翻转屏单反有哪些

超级马里奥c++代码

帮我写一个用于FX-20P-E编程器使用的喷泉的模拟控制指令表基于定时控制

A3P030的中文数据手册

libero soc 使用教程

会员权益专享

最新资源

用g代码写一个控制步进电机在限位a，b间移动，每次走1000步循环80次，每次间隔一秒