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Verilog

1364-2001

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IEEE Std 1364-2001

(Revision of

IEEE Std 1364-1995)

IEEE Standards

IEEE Standard Verilog

Hardware

Description Language

Published by

The Institute of Electrical and Electronics Engineers, Inc.

3 Park Avenue, New York, NY 10016-5997, USA

28 September 2001

IEEE Computer Society

Sponsored by the

Design Automation Standards Committee

IEEE Standards

Print: SH94921

PDF: SS94921

IEEE Standards

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iii

Introduction

(This introduction is not part of IEEE Std 1364-2001, IEEE Standard Verilog

Hardware Description Language.)

The Verilog

Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE

Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a

standard textual format for a variety of design tools, including verification simulation, timing analysis, test

analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language

of choice by an overwhelming number of IC designers.

Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,

and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is

essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in

which expressions of both variables and nets can continuously drive values onto nets, provide the basic

structural construct. Procedural assignments, in which the results of calculations involving variable and net

values can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod-

ules, each of which has an I/O interface, and a description of its function, which can be structural, behav-

ioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets.

The Verilog language is extensible via the Programming Language Interface (PLI) and the Verilog Proce-

dural Interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access

information contained in a Verilog HDL description of the design and facilitates dynamic interaction with

simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation

and CAD systems, customized debugging tasks, delay calculators, and annotators.

The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer-

sity in England under a contract to produce a test generation system for the British Ministry of Defense.

HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification

simulation, timing analysis, fault simulation, and test generation.

In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open

Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of Direc-

tors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE Working

Group was formed and after 18 months of focused efforts Verilog became an IEEE standard as IEEE Std

1364-1995.

After the standardization process was complete the 1364 Working Group started looking for feedback from

1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five year

effort to get a much better Verilog standard in IEEE Std 1364-2001.

Objective of the IEEE Std 1364-2001 effort

The starting point for the IEEE 1364 Working Group for this standard was the feedback received from the

IEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all

aspects of the language. Users at the higher levels wanted to expand and improve the language at the RTL

and behavioral levels, while users at the lower levels wanted improved capability for ASIC designs and

signoff. It was for this reason that the 1364 Working Group was organized into three task forces: Behavioral,

ASIC, and PLI.

The clear directive from the users for these three task forces was to start by solving some of the following

problems:

Consolidate existing IEEE Std 1364-1995

Verilog Generate statement

Multi-dimensional arrays

Enhanced Verilog file I/O

Re-entrant tasks

Standardize Verilog configurations

Enhance timing representation

Enhance the VPI routines

Achievements

Over a period of four years the 1364 Verilog Standards Group (VSG) has produced five drafts of the LRM.

The three task forces went through the IEEE Std 1364-1995 LRM very thoroughly and in the process of con-

solidating the existing LRM have been able to provide nearly three hundred clarifications and errata for the

Behavioral, ASIC, and PLI sections. In addition, the VSG has also been able to agree on all the enhance-

ments that were requested (including the ones stated above).

Three new sections have been added. Clause 13, Configuring the contents of a design, deals with configu-

ration management and has been added to facilitate both the sharing of Verilog designs between designers

and/or design groups and the repeatability of the exact contents of a given simulation session. Clause 15,

Timing checks, has been broken out of Clause 17, System tasks and functions, and details more fully

how timing checks are used in specify blocks. Clause 16, Backannotation using the Standard Delay Format

(SDF), addresses using back annotation (IEEE Std 1497-1999) within IEEE Std 1364-2001.

Extreme care has been taken to enhance the VPI routines to handle all the enhancements in the Behavioral

and other areas of the LRM. Minimum work has been done on the PLI routines and most of the work has

been concentrated on the VPI routines. Some of the enhancements in the VPI are the save and restart, simu-

lation control, work area access, error handling, assign/deassign and support for array of instances, generate,

and file I/O.

Work on this standard would not have been possible without funding from the CAS society of the IEEE and

Open Verilog International.

The IEEE Std 1364-2001 Verilog Standards Group organization

Many individuals from many different organizations participated directly or indirectly in the standardization

process. The main body of the IEEE Std 1364-2001 working group is located in the United States, with a

subgroup in Japan (EIAJ/1364HDL).

The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to be

approved by this group to be implemented. The three task forces focused on their specific areas and their

recommendations were eventually voted on by the IEEE Std 1364-2001 working group.

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