SmartFusion2和Spartan6的比较_smartfusion2

SmartFusion2

Spartan6

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KEY FIGHT: Xilinx Spartan-6T Devices vs SmartFusion2 SoC FPGAs

Winning with SmartFusion2 SoC FPGAs against Xilinx Spartan-6T Devices

Xilinx Spartan-6T FPGAs are produced on a 45-nm process, and claim to balance low risk, low cost and low power

Static power consumption is an order of magnitude higher than SmartFusion2 SoC FPGAs

The maximum transceiver speed is limited to 3.125 Gbps

Spartan-6T devices are susceptible to failure due to single event upsets (SEU) affecting configuration SRAM

Spartan-6T devices have no built-in design security

Spartan-6T FPGAs do not have an integrated hard processor core

We are comparing Spartan-6T FPGAs with SmartFusion2 SoC FPGAs as they are comparable in logic size

Xilinx Spartan-6 FPGAs

Xilinx’s Spartan-6T family of devices is designed to target low power, low cost applications that need high speed serial interfaces.

§ Spartan-6T FPGAs are SRAM based

§ Spartan-6T devices are built on a 45-nm SRAM process and use a 1.2 volt power supply.

§ Spartan-6T FPGAs integrate up to 8 transceivers that operate at up to 3.125 Gbps with 1 hard PCIe (PIPE) block

§ Spartan-6T FPGAs support high speed memory interfaces using Xilinx and Partner IP cores.

Device Cross Reference

Xilinx Spartan-6T FPGAs Microsemi Smartfusion2 SoC FPGAs

Part

Logic

Cells

Max

I/O

RAM

kbits

Math

Blocks

SERDES

(1)

Channels

PCIe

Endpoint

Part LEs

Max

I/O

RAM

kbits

Math

Blocks

SERDES

Channels

PCIe

Endpoint

M2S005 4,956 231 198 11 0 0

M2S010 9,744 237 400 22 4 1

M2S025 23,998 269 590 34 4 1

XC6SLX25T 24,050 250 229 38 2 1

XC6SLX45T 43,661 296 401 58 4 1

1 M2S050 48,672 377 1,314 72 8 2

XC6SLX75T 74,637 348 692 132 8 1

M2S080 82,232 574 3,040 160 8 2

XC6SLX100T 101,261 498 976 180 8 1

M2S120 120,348 574 4,500 240 16 4

XC6SLX150T 147,443 540 1,355 180 8 1

Feature Comparison

Features Xilinx Spartan-6T FPGAs Microsemi SmartFusion2 SoC FPGAs

Logic Architecture

Logic Cell = 6 Input Look Up Table + 2 Flip Flops

Carry Chain input and output

1 Slice = 4 Logic Cells

4 Input Look-Up Table + Register

Carry Chain input and output

12 logic module (LM)

per Cluster

Math Blocks

18 x 18 signed multipliers + 48 bit accumulator

48 bit output

Inputs and outputs optionally registered

18 x 18 signed multipliers + 44 bit accumulator

44 bit output

Inputs and outputs optionally registered

SERDES Channels

Up to 8 channels / lanes

2.5 or 3.2 Gbps each channel/lane

Up to 16 channels / lanes

5.0 Gbps each channel/lane

PCIe

1 Hard instantiation per device

Generation 1 (2.5 Gbps), 1, 2 or 4 lanes

Multiple hard instantiations per device

Generation 1 (2.5 Gbps) or 2 (5.0 Gbps), 1, 2 or 4

lanes

Integrated embedded

processor subsystem

None

ARM™Cortex™-M3 Processor

SEU protected Instruction Cache

SoC Peripherals

DDR Memory Interfaces

2 memory controller blocks

Operational at up to 800 Mbps

Hard instantiated DDR3 memory controllers

Operational at up to 667 Mbps

Security

Unique device identifier for readback

AES Bitstream encryption in select devices

State of the art security for root-of-trust applications

Non-volatile devices do not expose bitstream

Most effective design and data security functions

1,Smartfusion2 has more block ram resources than Spartan 6

2,little size of members of Smartfusion2 have more Math blocks than Spartan6

3.Smarfusion2 support PCIe gen1 or gen2 while Spartan 6 has PCIe gen1 only

4.Smarfusion2 has multi PCIe hard cores while Spartan 6 has one only

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