PowerPC架构E500MC内核详解

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"freescale的PowerPC架构的E500MC内核参考手册，是针对Freescale公司的E500MC处理器内核的详细技术文档，旨在为开发者和系统设计师提供全面的参考资料。该手册适用于所有版本的E500MC核心，涵盖了32位处理能力、多核支持等特性。手册由Freescale Semiconductor于2011年发布，其中包含了重要的知识产权声明和法律条款。" 本文档详细介绍Freescale的PowerPC架构E500MC内核，这是一个高性能、低功耗的处理器核心，广泛应用于嵌入式系统、工业控制以及网络设备等领域。E500MC的核心设计基于Power Architecture技术，这是一项开放标准的处理器架构，由Power.org授权并维护。 E500MC内核的特点包括： 1. **32位架构**：E500MC是一个32位处理器核心，提供了高效的指令处理能力，适用于多种复杂计算任务。 2. **多核支持**：E500MC支持多核配置，可以实现多个核心在同一芯片上协同工作，提高了系统的并行处理能力和性能。 3. **高性能**：E500MC内核设计考虑了高频率运行和低功耗的需求，提供高性能的同时，保持了较低的能源消耗。 4. **兼容性**：作为PowerPC架构的一部分，E500MC与Power Architecture指令集兼容，使得软件开发和移植更加便捷。 5. **扩展性**：E500MC允许设计者通过添加额外的硬件模块或扩展接口来定制特定应用的解决方案。 6. **错误检测与纠正**：通常集成有先进的错误检测和纠正机制，以确保系统稳定性和可靠性。 7. **嵌入式功能**：内核可能包含嵌入式内存管理单元（MMU）、浮点运算单元（FPU）和其他专用硬件加速器，以增强特定应用领域的性能。手册中可能涵盖以下内容： - 内核结构：详细描述E500MC的内部组件，如执行单元、寄存器、数据路径等。 - 指令集：列出E500MC支持的指令集，包括数据处理、分支、存储访问等操作。 - 总线接口：详述E500MC如何与其他系统组件通信，如系统总线、内存控制器等。 - 多核互连：说明多核配置下的同步、通信和资源共享机制。 - 片上外设：介绍内核中集成的片上外设，如中断控制器、计时器等。 - 能效管理：描述如何优化能源使用，包括低功耗模式和动态电压频率调整（DVFS）。 - 错误处理：讲解内核的错误检测和恢复机制。 - 开发工具支持：提供关于调试器、编译器和其他开发工具的信息。请注意，由于文档的版权限制，此处无法提供具体的手册内容，但这些概述应该能帮助读者理解E500MC内核的基本特性和功能。实际的手册将提供更深入的技术细节，对于设计和开发基于E500MC的系统至关重要。

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e500mc Core Reference Manual, Rev. 0

xvi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

10.4.3.1 Effect of Operand Placement on Performance .................................................... 10-16

10.5 Instruction Latency Summary...................................................................................... 10-17

10.6 Instruction Scheduling Guidelines............................................................................... 10-29

Chapter 11

Core Software Initialization Requirements

11.1 Core State and Suggested Software Initialization After Reset ...................................... 11-1

11.2 MMU State..................................................................................................................... 11-1

11.3 Register State ................................................................................................................. 11-1

11.3.1 GPRs .......................................................................................................................... 11-1

11.3.2 FPRs........................................................................................................................... 11-2

11.3.3 SPRs........................................................................................................................... 11-2

11.3.4 MSR and FPSCR ....................................................................................................... 11-3

11.4 Timer State..................................................................................................................... 11-3

11.5 L1 Cache State ............................................................................................................... 11-4

11.6 L2 Cache State ............................................................................................................... 11-5

11.7 Branch Target Buffer State............................................................................................. 11-5

Appendix A

Simplified Mnemonics

A.1 Overview......................................................................................................................... A-1

A.2 Subtract Simplified Mnemonics ..................................................................................... A-1

A.2.1 Subtract Immediate ..................................................................................................... A-1

A.2.2 Subtract ....................................................................................................................... A-2

A.3 Rotate and Shift Simplified Mnemonics......................................................................... A-2

A.3.1 Operations on Words .................................................................................................. A-2

A.4 Branch Instruction Simplified Mnemonics..................................................................... A-3

A.4.1 Key Facts about Simplified Branch Mnemonics ........................................................ A-4

A.4.2 Eliminating the BO Operand ...................................................................................... A-5

A.4.3 Incorporating the BO Branch Prediction .................................................................... A-6

A.4.4 The BI Operand—CR Bit and Field Representations................................................. A-7

A.4.4.1 BI Operand Instruction Encoding........................................................................... A-8

A.4.4.1.1 Specifying a CR Bit............................................................................................ A-8

A.4.4.1.2 The crS Operand .............................................................................................. A-10

A.4.5 Simplified Mnemonics that Incorporate the BO Operand ........................................ A-10

A.4.5.1 Examples that Eliminate the BO Operand.............................................................A-11

A.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI

with crS) ............................................................................................................... A-14

e500mc Core Reference Manual, Rev. 0

Freescale Semiconductor xvii

Contents

Paragraph

Number Title

Page

Number

A.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions:

Examples .......................................................................................................... A-16

A.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions:

Listings ............................................................................................................. A-16

A.5 Compare Word Simplified Mnemonics ........................................................................ A-18

A.6 Compare Double-word Simplified Mnemonics............................................................ A-19

A.7 Condition Register Logical Simplified Mnemonics ..................................................... A-20

A.8 Trap Instructions Simplified Mnemonics ..................................................................... A-20

A.9 Simplified Mnemonics for Accessing SPRs ................................................................. A-22

A.10 Recommended Simplified Mnemonics......................................................................... A-23

A.10.1 No-Op (nop) ............................................................................................................. A-23

A.10.2 Load Immediate (li) .................................................................................................. A-23

A.10.3 Load Address (la) ..................................................................................................... A-23

A.10.4 Move Register (mr) .................................................................................................. A-24

A.10.5 Complement Register (not) ...................................................................................... A-24

A.10.6 Move to Condition Register (mtcr).......................................................................... A-24

A.10.7 Sync (sync) ............................................................................................................... A-24

A.10.8 Integer Select (isel) ................................................................................................... A-24

A.10.9 TLB Invalidate Local Indexed.................................................................................. A-25

e500mc Core Reference Manual, Rev. 0

Freescale Semiconductor -xix

Figures

Figure

Number Title

Page

Number

Figures

1-1 e500mc Block Diagram .......................................................................................................... 1-3

1-2 Example Partitioning Scenario of a Multicore Integrated Device .......................................... 1-4

1-3 GPR Issue Queue (GIQ) ......................................................................................................... 1-9

1-4 Three-Stage Load/Store Unit ................................................................................................ 1-11

2-1 Machine State Register (MSR) ............................................................................................. 2-11

2-2 Processor Version Register (PVR) ........................................................................................ 2-12

2-3 System Version Register (SVR)............................................................................................ 2-13

2-4 Relationship of Timer Facilities to the Time Base................................................................ 2-13

2-5 (Guest) Interrupt Vector Offset Registers ((G)IVORs)......................................................... 2-17

2-6 (Guest) Exception Syndrome Register (ESR/GESR) ........................................................... 2-19

2-7 Machine Check Syndrome Register (MCSR)....................................................................... 2-22

2-8 Branch Unit Control and Status Register (BUCSR) ............................................................. 2-26

2-9 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-26

2-10 Core Device Control and Status Register 0 (CDCSR0) Format ........................................... 2-28

2-11 L1 Cache Control and Status Register 0 (L1CSR0) Fields Implemented on e500mc.......... 2-29

2-12 L1 Cache Control and Status Register 1 (L1CSR1) Fields Implemented on the e500mc .... 2-31

2-13 L1 Cache Control and Status Register 2 (L1CSR2) Fields Implemented on the e500mc .... 2-33

2-14 L1 Cache Configuration Register 0 (L1CFG0) Fields Implemented on the e500mc ........... 2-34

2-15 L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 2-35

2-16 L2 Cache Configuration Register 0 (L2CFG0)..................................................................... 2-36

2-17 L2 Cache Control and Status Register (L2CSR0)................................................................. 2-37

2-18 L2 Cache Control and Status Register 1 (L2CSR1).............................................................. 2-40

2-19 L2 Cache Error Disable Register (L2ERRDIS).................................................................... 2-41

2-20 L2 Cache Error Detect Register (L2ERRDET) .................................................................... 2-43

2-21 L2 Cache Error Interrupt Enable Register (L2ERRINTEN) ................................................ 2-44

2-22 L2 Cache Error Control Register (L2ERRCTL)................................................................... 2-45

2-23 L2 Cache Error Attribute Register (L2ERRATTR) .............................................................. 2-46

2-24 L2 Cache Error Injection Control Register (L2ERRINJCTL).............................................. 2-47

2-25 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-49

2-26 MMU Configuration Register (MMUCFG) ......................................................................... 2-50

2-27 TLB Configuration Registers 0 and 1 (TLB0CFG, TLB1CFG) ........................................... 2-50

2-28 MAS Register 0 (MAS0) ...................................................................................................... 2-52

2-29 MAS Register 1 (MAS1) ...................................................................................................... 2-53

2-30 MAS Register 2 (MAS2) ...................................................................................................... 2-54

2-31 MAS Register 3 (MAS3) ...................................................................................................... 2-55

2-32 MAS Register 4 (MAS4) ...................................................................................................... 2-56

2-33 MAS Register 5 (MAS5) ...................................................................................................... 2-57

2-34 MAS Register 6 (MAS6) ...................................................................................................... 2-58

2-35 MAS Register 7 (MAS7) ...................................................................................................... 2-58

2-36 MAS Register 8 (MAS8) Format.......................................................................................... 2-59

2-37 External PID Load Context (EPLC) Format......................................................................... 2-60

e500mc Core Reference Manual, Rev. 0

-xx Freescale Semiconductor

Figures

Figure

Number Title

Page

Number

2-38 External PID Store Context (EPSC) Format......................................................................... 2-61

2-39 Debug Control Register 0 (DBCR0)..................................................................................... 2-62

2-40 Debug Control Register 1 (DBCR1)..................................................................................... 2-64

2-41 Debug Control Register 2 (DBCR2)..................................................................................... 2-66

2-42 Debug Control Register 4 (DBCR4)..................................................................................... 2-68

2-43 Debug Status Register Write Register (DBSRWR) .............................................................. 2-69

2-44 Debug Status Register (DBSR)............................................................................................. 2-69

2-45 Instruction Address Compare Registers (IAC1-IAC2)......................................................... 2-72

2-46 Data Address Compare Registers (DAC1–DAC2)............................................................... 2-72

2-47 Nexus SPR Configuration Register (NSPC)......................................................................... 2-73

2-48 Nexus SPR Data Register (NSPD)........................................................................................ 2-73

2-49 Debug Event Register (DEVENT)........................................................................................ 2-74

2-50 Debug Data Acquisition Message Register (DDAM)........................................................... 2-75

2-51 Nexus Process ID Register.................................................................................................... 2-75

2-52 Performance Monitor Global Control Register 0 (PMGC0)/

User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 2-77

2-53 Local Control A Registers (PMLCa0–PMLCa3)/

User Local Control A Registers (UPMLCa0–UPMLCa3) .............................................. 2-78

2-54 Local Control B Registers (PMLCb0–PMLCb3)/

User Local Control B Registers (UPMLCb0–UPMLCb3) .............................................. 2-79

2-55 Performance Monitor Counter Registers (PMC0–PMC3)/

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................. 2-82

5-1 Cache/Core Interface Unit Integration.................................................................................... 5-5

5-2 L1 Data Cache Organization...................................................................................................5-7

5-3 L1 Instruction Cache Organization ......................................................................................... 5-8

5-4 PLRU Replacement Algorithm............................................................................................. 5-25

6-1 Effective-to-Real Address Translation Flow in e500mc......................................................... 6-4

6-2 Forming a Virtual Address Using External PID ..................................................................... 6-5

6-3 Virtual Address and TLB-Entry Compare Process ................................................................. 6-6

6-4 Two-Level MMU Structure..................................................................................................... 6-7

6-5 L1 MMU TLB Organization................................................................................................... 6-9

6-6 L2 MMU TLB Organization................................................................................................. 6-10

6-7 Round Robin Replacement for TLB0 ................................................................................... 6-11

6-8 L1 MMU TLB Relationships with L2 TLBs ........................................................................ 6-12

7-1 Relationship of Timer Facilities to Time Base........................................................................ 7-2

8-1 Core Activity State Diagram................................................................................................... 8-4

8-2 Core Power Management Handshaking.................................................................................. 8-5

9-1 External Debug Control Register 0 (EDBCR0)...................................................................... 9-3

9-2 External Debug Status Register 0 (EDBSR0)......................................................................... 9-4

9-3 External Debug Status Register Mask 0 (EDBSRMSK0) ...................................................... 9-6

9-4 External Debug Status Register 1 (EDBSR1)......................................................................... 9-7

e500mc Core Reference Manual, Rev. 0

Freescale Semiconductor -xxi

Figures

Figure

Number Title

Page

Number

9-5 Processor Run Status Register (PRSR) ................................................................................... 9-8

9-6 Extended External Debug Control Register 0 (EEDCR0) ...................................................... 9-9

9-7 Nexus Development Control Register 1 (DC1) .................................................................... 9-10

9-8 Nexus Development Control Register 2 (DC2) .................................................................... 9-12

9-9 Nexus Development Control Register 4 (DC4) .................................................................... 9-13

9-10 Nexus Watchpoint Trigger Register 1................................................................................... 9-14

9-11 Nexus Watchpoint Mask Register......................................................................................... 9-15

9-12 Nexus Overrun Control Register........................................................................................... 9-16

9-13 IJAM Configuration Register................................................................................................ 9-18

9-14 IJAM Instruction Register (IJIR) .......................................................................................... 9-19

9-15 IJAM Data Registers (IJDATA0–IJDATA1)......................................................................... 9-19

9-16 Performance Monitor Counter Capture Registers (PMCC0–PMCC3)................................. 9-20

9-17 Program Counter Capture Register (PCC)............................................................................ 9-20

9-18 Debug/Expert Resource Access ............................................................................................ 9-36

9-19 Source ID Field Structure...................................................................................................... 9-54

9-20 Time Stamp Field Components............................................................................................. 9-54

9-21 Data Trace Address Field Components................................................................................. 9-64

9-22 Data Trace Full Address Reconstruction .............................................................................. 9-65

9-23 Watchpoint Hit Field ............................................................................................................. 9-70

9-24 Detailed View: Core Performance Monitor Counters 0 through 3 ....................................... 9-72

9-25 Core Performance Monitor Capture Capability .................................................................... 9-75

10-1 GPR Issue Queue (GIQ) ....................................................................................................... 10-4

10-2 Branch Completion (LR/CTR Write-Back) ........................................................................ 10-13

10-3 Updating Branch History .................................................................................................... 10-14

A-1 Branch Conditional (bc) Instruction Format.......................................................................... A-4

A-2 BO Field (Bits 6–10 of the Instruction Encoding)................................................................. A-5

A-3 BI Field (Bits 11–14 of the Instruction Encoding)................................................................. A-8

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