VHDL数字电路设计教程第5章习题参考答案

第 5 章习题参考答案

Problem 5.1

library ieee;

use ieee.std_logic_1164.all;

package my_data_type is

constant m: integer :=8;

type vector_array is array (natural range<>) of

std_logic_vector(m-1 downto 0);

port( datain: in vector_array(0 to n-1) ;

sel: in integer range 0 to n-1;

dataout: out std_logic_vector( m-1 downto 0));

end;

architecture bhv of n_mux is

begin

dataout<=datain(sel);

end;

Problem 5.2

方法一：利用简单赋值语句设计

architecture bhv of priority_encoder is

begin

y(2)<=x(7) or x(6) or x(5) or x(4);

y(1)<=x(7) or x(6) or (( not x(5) and not x(4)) and (x(3) or x(2)));

y(0)<=x(7) or (not x(6) and (x(5) or (not x(4) and (x(3) or (not x(2) and

x(1))))));

end;

方法二：利用 WHEN 语句设计

library ieee;

use ieee.std_logic_1164.all;