![](https://csdnimg.cn/release/download_crawler_static/3979565/bg1.jpg)
CPCI_bus
NF2_DMA
Nf2_reg_grp(1)
Cpu_dma_queue[0] Cpu_dma_queue[1] Cpu_dma_queue[2]
Cpu_dma_queue[3]
Cpu_add_rm_hdr[0] Cpu_add_rm_hdr[1] Cpu_add_rm_hdr[2] Cpu_add_rm_hdr[3]
Mac_group[0]
Mac_group[1] Mac_group[2] Mac_group[3]
RGMII_0 RGMII_0 RGMII_0 RGMII_0
SPARTAN 2 芯片
PHY 芯片1 PHY 芯片2
Sram芯片1
Sram芯片2
Sram控制器
Sram_addr
Sram_we
Sram_bw
Sram_tri_en
Sram_data
Sram_reg_req
Sram_reg_rd_wr_L
Sram_reg_addr
Sram_reg_wr_data
Sram_reg_ack
Sram_reg_rd_data
wr_0_req
Wr_0_data
Rd_0_req
Rd_0_addr
Rd_0_data
Rd_0-ack
Rd_0_vld
Wr_0_ack
wr_0_addr
Txd
tx_ctl txc rxd Rx_ctl rxc
Txd
tx_ctl txc rxd Rx_ctl rxc
Txd
tx_ctl txc rxd Rx_ctl rxc
Txd
tx_ctl txc rxd Rx_ctl rxc
txd
Tx
_en
Tx
_er
crs
Rx
_d
Rx
_dv
Rx
_er
col
txd
Tx_
en
Tx
_er
crs
Rx
_d
Rx
_dv
Rx
_er
col
txd
Tx
_en
Tx
_er
crs
Rx
_d
Rx
_dv
Rx
_er
col
txd
Tx
_en
Tx
_er
crs
Rx
_d
Rx
_dv
Rx
_er
col
In
_data
In
_rdy
In
_ctrl
Out
_wr
Out
_ctrl
Out_
rdy
Out
_data
In
_wr
In
_data
In
_rdy
In
_ctrl
Out
_wr
Out
_ctrl
Out_
rdy
Out
_data
In
_wr
In
_data
In
_rdy
In
_ctrl
Out
_wr
Out
_ctrl
Out_
rdy
Out
_data
In
_wr
In
_data
In
_rdy
In
_ctrl
Out
_wr
Out
_ctrl
Out_
rdy
Out
_data
In
_wr
Rd_
wr_l
req addr
Wr_
data
Rd_
data
Data_
Tri_en
Wr_rdyRd_rdy
Rd
_vld
Rd
_data
Fifo_
rd_en
Fifo
_empty
Rd_wr_l
Reg
_addr
Reg_wr
_data
Dma_reg_req
Dma_reg_addr
Dma_reg_wr_data
Dma_reg_rd_wr_L
In
_data
In
_ctrl
In
_rdy
Out
_data
Out
_ctrl
Out
_wr
Out
_rdy
In
_wr
In
_data
In
_ctrl
In
_rdy
Out
_data
Out
_ctrl
Out
_wr
Out
_rdy
In
_wr
In
_data
In
_ctrl
In
_rdy
Out
_data
Out
_ctrl
Out
_wr
Out
_rdy
In
_wr
In
_data
In
_ctrl
In
_rdy
Out
_data
Out
_ctrl
Out
_wr
Out
_rdy
In
_wr
rx
_data
rx
_ctrl
rx
_rdy
tx
_data
tx
_ctrl
tx
_wr
tx
_rdy
rx
_wr
rx
_data
rx
_ctrl
rx
_rdy
tx
_data
tx
_ctrl
tx
_wr
tx
_rdy
rx
_wr
rx
_data
rx
_ctrl
rx
_rdy
tx
_data
tx
_ctrl
tx
_wr
tx
_rdy
rx
_wr
rx
_data
rx
_ctrl
rx
_rdy
tx
_data
tx
_ctrl
tx
_wr
tx
_rdy
rx
_wr
Dma_op
_code_req
Dma_op_
Queue_id
Dma_vld
_c2n
Dma_data
_c2n
Dma_dest_q_
nearly_full_c2n
Dma_op
_ack
Dma_vld
_n2c
Dma_data
_n2c
Dma_dest_q_
Nearly_full_n2c
Dma_data
_tri_en
NF2_m
dio
Phy_mdc
phy_mdio
Device
_id_reg
Core_256kb_0_reg_grp
Core_4mb_reg_grp
Core_4mb_
reg_req_1
Core_4mb_
Reg_rd_wr_L_1
Core_4mb_
Reg_addr_1
Core_4mb_
Reg_ack_1
Core_4mb_reg
_rd_data_1
Core_reg_
Wr_data_1
Reg_ack
Reg_rd_data
reg_req
reg_rd_wr
_L
reg_addr
reg_wr_
data
说明:
图中红颜色的部分表示的是开
发板上提供的实际的外围芯
片,其他部分为NETFPGA的V2
芯片内部的电路框图。
wr
Wr
_data
Nearly
_full
pkt
_avail
Rd
_data
Rd
_ctrl
Rd
Wr
_ctrl
wr
Wr
_data
Nearly
_full
pkt
_avail
Rd
_data
Rd
_ctrl
Rd
Wr
_ctrl
wr
Wr
_data
Nearly
_full
pkt
_avail
Rd
_data
Rd
_ctrl
Rd
Wr
_ctrl
wr
Wr
_data
Nearly
_full
pkt
_avail
Rd
_data
Rd
_ctrl
Rd
Wr
_ctrl
nf2_reg_grp(2)
注意:
nf2_reg_grp(2)和
nf2_reg_grp(1)
是同一个模块
Udp_
Reg_rd_
wr_L
Udp_
reg_addr
Udp_reg_
wr_data
Udp_reg_
rd_data
Udp_
reg_ack
udp_
reg_req
Mac_grps
[0:3]
Cpu_grps
[0:3]
local_reg_req
{16}
Local_reg_rd_wr_L
{16}
Local_reg_addr
{256}
Local_reg_wr_data
{512}
Local_reg_ack
{16}
Local_reg_rd_data
{512}