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FE2.1 7口USBHUB芯片手册
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更新于2023-06-25
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FE2.1 是一款7口USBHUB芯片,USB2.0接口,可扩展7路高速USB2.0接口。
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USB 2.0 7-Port Hub
FE2.1
USB 2.0 HIGH SPEED 7-PORT HUB CONTROLLER
INTRODUCTION
The FE2.1 is a highly integrated, high quality,
high performance, low power consumption, yet
low overall cost solution for USB 2.0 High Speed
7-Port Hub.
It adopts Multiple Transaction Translator (MTT)
architecture to explore the maximum possible
throughput. Six, instead of two, non-periodic
transaction buffers are used to minimize potential
traffic jamming. The whole design is based on
state-machine-control to reduce the response
delay time; no micro controller is used in this
chip.
To guarantee high quality, the whole chip is
covered by Test Scan Chain – include even the
high speed (480MHz) modules, so that all the
logic components could be fully tested before
shipping. Special Build-In-Self-Test mode is
designed to exercise all high, full, and low speed
Analog Front End (AFE) components in the
packaging and testing stages as well.
Low power consumption is achieved by using
0.1
8μ
m technology and comprehensive
power/clock control mechanism. Most part of the
chip will not be clocked unless needed.
FEATURES
Low power consumption
□
155 mA when seven downstream facing
ports enabled in High-Speed mode;
□
66 mA when one downstream facing
port enabled in High-Speed mode;
Fully compliant with Universal Serial Bus
Specification Revision 2.0 (USB 2.0);
□
Upstream facing port supports High-
Speed (480MHz) and Full-Speed
(12MHz) modes;
□
7 downstream facing ports support
High-Speed (480MHz), Full-Speed
(12MHz), and Low-Speed (1.5MHz)
modes;
Integrated USB 2.0 Transceivers;
Integrated upstream 1.5KΩ pull-up,
downstream 15KΩ pull-down, and serial
resisters;
Integrated 5V to 3.3V and 1.8V regulator.
Integrated Power-On-Reset circuit;
Integrated 12MHz Oscillator with feedback
resister and crystal load capacitor;
Integrated 12MHz-to-480MHz Phase Lock
Loop (PLL);
Multiple Transaction Translator (MTT) –
□
One TT for each downstream port;
Feb. 27, 2009 Preliminary, Confidential, Subject to Change Without Notice 1
USB 2.0 7-Port Hub
□
Alternate Interface 0 for Single-TT, and
Alternate Interface 1 for Multiple-TT;
□
Each TT could handle 64 periodic
Start-Split transactions, 32 periodic
Complete-Split transactions, and 6
none-periodic transactions;
Support Self-Powered Mode only;
Board configured options –
□
Ganged or Individual Power Control
Mode select;
□
Global, Multiple Ganges, or Individual
Over-Current Protection Mode select;
□
Removable or Non-Removable
Downstream Devices configuration;
□
Number of Downstream Ports;
EEPROM configured options –
□
Vendor ID, Product ID, & Device
Release Number;
□
Removable or Non-Removable
Downstream Devices configuration;
□
Serial Number; and
□
Number of Downstream Ports;
Comprehensive status indicators support:
□
Standard downstream port status
indicators (Green and Amber LED
control for each downstream port);
□
Hub Active/Suspend indicator LED.
Feb. 27, 2009 Preliminary, Confidential, Subject to Change Without Notice 2
USB 2.0 7-Port Hub
BLOCK DIAGRAM
Feb. 27, 2009 Preliminary, Confidential, Subject to Change Without Notice 3
Fig. 1: Block Diagram
Down-
stream
PHY #1
Down-
stream
PHY #2
∙∙∙∙∙
Down-
stream
PHY #7
Upstream
PHY
Routing Switch
Data
Transmit
Data
Recovery &
Elasticity
Buffer
PLL
(x40)
3.3V & 1.8V Regulator
POR
USB Multi-port Transceiver Macro Cell
SIE
Downstream
Port
Controllers
Upstream
Port
Controller
Transaction Translator
Full/Low-Speed Handler
Transaction Translator
High-Speed Handler
Hub Controller
LED
Controller
Unified Transaction
Translator Buffer (14KB)
USB 2.0
Hub
Controller
OSC
12MHz
Crystal
To Downstream
Devices
To Upstream
Host/Hub
Port
Indicators
EEPROM,
Hub Activity
LED
Over Current
Detection
Power Switch
Control
USB 2.0 7-Port Hub
PACKAGE I – 64-PIN LQFP
(Body Size: 10x10 mm)
PIN ASSIGNMENT
Feb. 27, 2009 Preliminary, Confidential, Subject to Change Without Notice 4
Fig. 2: 64-pin LQFP Pin Assignment
1
17
16
32
33
48
4964
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