SPI 协议 2008-08-11 19:57
The Serial Peripheral Interface Bus or SPI (often pronounced "es-pē-ī" [IPA: ɛs pi: 'aɪ] or "spy"
[IPA: spaɪ]) bus is a synchronous serial data link standard named by Motorola that operates in full
duplex mode. Devices communicate in master/slave mode where the master device initiates the
data frame. Multiple slave devices are allowed with individual slave select (chip select) lines.
Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial
buse
spi 协议是一种同步的串行数据连接标准,由摩托罗拉公司命名,可工作与全双工方式。
相关通讯设备可工作与 m/s 模式。主设备发起数据帧,允许多个从设备的存在。每个重设备
有独立的片选信号。SPI 一般来说是四线串行总线结构,不同于三线两线或者一线的串行总
线。
interface 接口:
The SPI bus specifies four logic signals. 定义四个信号逻辑
SCLK — Serial Clock (output from master) 时钟(主设备发出)
MOSI/SIMO — Master Output, Slave Input (output from master)数据信号线 mosi(主设备发
出)
MISO/SOMI — Master Input, Slave Output (output from slave) 数据信号线(从设备)
SS — Slave Select (active low; output from master) 片选信号
Alternative naming conventions are also widely used:可选择的其他常用命名方式
SCK, CLK — Serial Clock (output from master)
SDI, DI, SI — Serial Data In
SDO, DO, SO — Serial Data Out
nCS, CS, nSS, STE — Chip Select, Slave Transmit Enable (active low; output from master)
The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be connected to SDI
on the slave, and vice-versa.
SPI port pin names for particular IC products may differ from those depicted in these illustrations.
spi 的 ic 产品中 i 端口管脚命名可能同上面不一样。
Operation 操作
The SPI bus can operate with a single master device and with one or more slave devices.
spi 总线可以操作与一个主设备多个从设备的模式
If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some
slaves require the falling edge (high->low transition) of the slave select to initiate an action such
as the MAX1242 by Maxim, an ADC, that starts conversion on said transition. With multiple slave
devices, an independent SS signal is required from the master for each slave device.
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