没有合适的资源?快使用搜索试试~ 我知道了~
首页TLK1521原理资料
TLK1521原理资料
5星 · 超过95%的资源 需积分: 17 10 下载量 20 浏览量
更新于2023-07-03
评论
收藏 489KB PDF 举报
讲诉了TLK1521的各种原理,以及使用方法,在光模块发送接收数据后的传输的用法
资源详情
资源评论
资源推荐
SLLS591C− OCTOBER 2003 − REVISED JULY 2007
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Hot Plug Protection
D 0.5 to 1.3 Gigabits Per Second (Gbps)
Serializer/Deserializer
D High-Performance 64-Pin HTQFP Thermally
Enhanced Package (PowerPAD)
D 2.5-V Power Supply for Low Power
Operation
D Selectable Signal Preemphasis for Serial
Output
D Interfaces to Backplane, Copper Cables, or
Optical Converters
D Lock Indication and Sync Mode for Fast
Initialization
D 18-Bit Parallel Busses for Flexible Interface
Applications
D On-chip PLL Provides Clock Synthesis
From Low-Speed Reference
D Receiver Differential Input Thresholds
200 mV Min
D Rated for Industrial Temperature Range
D Typical Power: 288 mW at 1.3 Gbps
D Ideal for High-Speed Backplane
Interconnect and Point-to-Point Data Link
D Passive Receive Equalizer
V
DD
RXD3
RXD4
RXD5
RXD6
GND
RXD7
RX_CLK
RXD8
RXD9
V
DD
RXD10
RXD11
RXD12
RXD13
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
DD
TXD3
TXD4
TXD5
GND
TXD6
TXD7
GTX_CLK
V
DD
TXD8
TXD9
TXD10
GND
TXD11
TXD12
TXD13
RXD1
DINRXP
63 62 61 60 5964 58
TXD0
GNDA
DOUTTXP
DOUTTXN
GNDA
PREEMPH
LOCKB
TESTEN
GND
RXD17
TXD15
TXD16
LOOPEN
TXD17
DD
ENABLE
SYNC
56 55 5457 53 52
TXD14
DINRXN
GNDA
51 50 49
RXD16
RXD15
RXD14
RXD0
RXD2
TXD2
TXD1
GND
V
DDA
V
DDA
V
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Copyright 2003 − 2007, Texas Instruments Incorporated
!"# $%!!& # %'$# (#&
!(%$ $!" &$$# &! )& &!" &*# !%"&
#(#!( +#!!#, !(%$ !$&- (& &$&#!', $'%(&
&- #'' #!#"&&!
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
SLLS591C− OCTOBER 2003 − REVISED JULY 2007
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The TLK1521 is a member of the WizardLink family of multi-gigabit transceivers, intended for use in high-speed
bidirectional point-to-point data transmission systems. The TLK1521 supports an effective serial interface
speed of 500 Mbps to 1.3 Gbps, providing up to 1.17 Gbps of data bandwidth.
The primary application of the TLK1521 is to provide high-speed I/O data channels for point-to-point baseband
data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be
printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is
dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The TLK1521 can also be used to replace parallel data transmission architectures by providing a reduction in
the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is
delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance
backplane, or an optical link. The data is then reconstructed into its original parallel format. It offers significant
power and cost savings over current solutions, as well as scalability for higher data rate in the future.
The TLK1521 performs the data parallel-to-serial, serial-to-parallel conversion, and clock extraction functions
for a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.3 Gbps.
The transmitter latches 18-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The
18-bit parallel data is internally encoded into 20 bits by framing the 18-bit data with a start and a stop bit. The
resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The
receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit
wide parallel data to the recovered clock (RX_CLK). It then extracts the 18 bits of data from the 20-bit wide data
resulting in 18 bits of parallel data at the receive data pins (RXD0−17). This results in an effective data payload
of 450 Mbps to 1.17 Gbps (18 bits data x GTX_CLK frequency).
The TLK1521 is housed in a high performance, thermally enhanced, 64-pin HTQFP PowerPAD package. Use
of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which
is an exposed die pad on the bottom of the device, is a metallic, thermal, and electrical conductor. It is strongly
recommended that the TLK1521 PowerPAD
be soldered to the grounded thermal land on the board, since the
PowerPAD also constitutes a major electrical ground connection for the TLK1521. All ac performance
specifications in this data sheet are measured with the PowerPAD soldered to the test board.
The TLK1521 provides an internal loopback capability for self-test purposes. Serial data from the serializer is
passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.
The TLK1521 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low and
places the parallel side output signal pins, DOUTTXP and DOUTTXN, into a high-impedance state during power
up.
The TLK1521 uses a 2.5-V supply. The I/O section is 3-V compatible. The TLK1521 is characterized for
operation from −40°C to 85°C.
SLLS591C− OCTOBER 2003 − REVISED JULY 2007
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
LOOPEN
DINRXN
DINRXP
PREEMPH
Recovered
Clock
DOUTTXP
DOUTTXN
LOCKB
RX_CLK
TD(0−17)
RD(0−17)
Multiplying
Clock
Synthesizer
Interpolator and
Clock Recovery
ENABLE
18
TESTEN
20
Controls:
PLL,Bias,Rx,
Tx
18-Bit
Register
18-Bit
Register
GTX_CLK
Parallel to
Serial
MUX
MUX
Serial to
Parallel
20
18
Start/Stop
Decoder
Bit
Clock
Bit
Clock
Start/Stop
Encoder
transmit interface
The transmitter portion registers valid incoming 18-bit wide data (TXD[0:17]) on the rising edge of GTX_CLK.
The data is then framed with a start and a stop bit, serialized and transmitted sequentially over the differential
high-speed I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times
creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on
both the rising and falling edges of the bit clock providing a serial data rate that is 20 times the reference clock.
Data is transmitted LSB (D0) first.
transmit data bus
The transmit bus interface accepts 18-bit wide single-ended TTL parallel data at the TXD[0:17] pins. Data is
valid on the rising edge of GTX_CLK. The GTX_CLK is used as the word clock. The data and clock signals must
be properly aligned as shown in Figure 1. Detailed timing information can be found in the TTL input electrical
characteristics table.
SLLS591C− OCTOBER 2003 − REVISED JULY 2007
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GTX_CLK
TXDn
t
su
t
h
Figure 1. Transmit Timing Waveform
transmission latency
The data transmission latency of the TLK1521 is defined as the delay from the initial 18-bit word load to the serial
transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process
variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.
Figure 2 illustrates the timing relationship between the transmit data bus, GTX_CLK, and serial transmit pins.
16-Bit Word to Transmit
Transmitted 20-Bit Word
DOUTTXP,
DOUTTXN
TXD(0−17)
GTX_CLK
t
d(Tx
latency)
Figure 2. Transmitter Latency
start/stop framing logic
All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving
PLL has a minimal number of transitions in which to stay locked onto the data stream. The signal coding also
provides a mechanism for the receiver to identify the byte boundary for correct deserialization. The TLK1521
wraps a start bit (1) and a stop bit (0) around the 18-bit data payload as shown in Figure 3. This is transparent
to the user, as the TLK1521 internally adds the framing bits to the data such that the user reads and writes actual
18-bit data.
start/stop framing logic (continued)
...
Start
Bit
Stop
Bit
TD0 TD1 TD16 TD17 Start
Bit
Stop
Bit
Figure 3. Serial Output Data Stream With Start and Stop Bit
SLLS591C− OCTOBER 2003 − REVISED JULY 2007
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
parallel-to-serial
The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the framing logic and
converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally
generated bit clock, which is 10 times the GTX_CLK input frequency. The LSB (TD0) is transmitted first as
shown in Figure 3.
high-speed data output
The high-speed data output driver consists of a PECL-compatible differential pair that can be optimized for a
particular transmission line impedance and length. The line can be directly coupled or ac coupled. See Figure 11
and Figure 12 for termination details. No external pullup or pulldown resistors are required.
The TLK1521 provides a selectable signal preemphasis option for driving lossy media. When signal
preemphasis is enabled, the first bit of a run length of same-value bits is driven to a larger output swing, which
precompensates for signal inter-symbol interference (ISI) in lossy media, such as copper cables or printed
circuit board traces.
receive interface
The receiver portion of the TLK1521 accepts 20-bit framed differential serial data. The interpolator and clock
recovery circuit locks to the data stream and extracts the bit rate clock. This recovered clock is used to retime
the input data stream. The serial data is then aligned to the 20-bit word boundary by finding the start/stop bits
and the 18-bit data is output on a 18-bit wide parallel bus synchronized to the extracted receive clock.
receive data bus
The receive bus interface drives 18-bit wide single-ended TTL parallel data at the RXD[0:17] pins. Data is valid
on the rising edge of RX_CLK. The RX_CLK is used as the recovered word clock. The data and clock signals
are aligned as shown in Figure 4. Detailed timing information can be found in the TTL output switching
characteristics table.
RX_CLK
RXDn
t
su
t
h
Figure 4. Receive Timing Waveform
剩余22页未读,继续阅读
whut_tx
- 粉丝: 0
- 资源: 2
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- zigbee-cluster-library-specification
- JSBSim Reference Manual
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论2