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synplify user guide
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synplify pro for lattice user guide in english.
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Synopsys FPGA Synthesis
Synplify and Synplify Pro for Lattice
User Guide
February 2010
LO
2 Synopsys FPGA Synthesis User Guide, February 2010
Disclaimer of Warranty
Synopsys, Inc. makes no representations or warranties, either expressed or
implied, by or with respect to anything in this manual, and shall not be liable
for any implied warranties of merchantability or fitness for a particular
purpose of for any indirect, special or consequential damages.
Copyright Notice
Copyright © 2010 Synopsys, Inc. All Rights Reserved.
Synopsys software products contain certain confidential information of
Synopsys, Inc. Use of this copyright notice is precautionary and does not
imply publication or disclosure. No part of this publication may be repro-
duced, transmitted, transcribed, stored in a retrieval system, or translated
into any language in any form by any means without the prior written
permission of Synopsys, Inc. While every precaution has been taken in the
preparation of this book, Synopsys, Inc. assumes no responsibility for errors
or omissions. This publication and the features described herein are subject
to change without notice.
Trademarks
Registered Trademarks (®)
Synopsys, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra,
CATS, Certify, Design Compiler, DesignWare, Formality, HDL Analyst,
HSPICE, Identify, iN-Phase, Leda, MAST, ModelTools, NanoSim, OpenVera,
PathMill, Physical Compiler, PrimeTime, SiVL, SCOPE, Simply Better Results,
SNUG, SolvNet, Synplicity, the Synplicity logo, Synplify, Synplify Pro,
Synthesis Constraints Optimization Environment, TetraMAX, VCS, Vera, and
YIELDirector are registered trademarks of Synopsys, Inc.
Trademarks (™)
AFGen, Apollo, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia,
Columbia-CE, Confirma, Cosmos, CosmosLE, CosmosScope, CRITIC, DC
Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, Design-
erHDL, DesignPower, Direct Silicon Access, Discovery, Eclypse, Encore,
EPIC, Galaxy, HANEX, HAPS, HapsTrak, HDL Compiler, Hercules, Hierar-
Synopsys FPGA Synthesis User Guide, February 2010 3
chical Optimization Technology, High-performance ASIC Prototyping System,
HSIM, HSIM
plus
, i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Jupiter,
Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library
Compiler, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource,
Module Compiler, MultiPoint, Physical Analyst, Planet, Planet-PL, Polaris,
Power Compiler, Raphael, Saturn, Scirocco, Scirocco-i, Star-RCXT,
Star-SimXT, System Compiler, System Designer, Taurus, TotalRecall,
TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are
trademarks of Synopsys, Inc.
Service Marks (
SM
)
MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.
SystemC is a trademark of the Open SystemC Initiative and is used under
license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a
registered trademark of SabreMark Limited Partnership and is used under
license. All other product or company names may be trademarks of their
respective owners.
Restricted Rights Legend
Government Users: Use, reproduction, release, modification, or disclosure of
this commercial computer software, or of any related documentation of any
kind, is restricted in accordance with FAR 12.212 and DFARS 227.7202, and
further restricted by the Synopsys Software License and Maintenance
Agreement. Synopsys, Inc., Synplicity Business Group, 600 West California
Avenue, Sunnyvale, CA 94086, U. S. A.
February 2010
LO
4 Synopsys FPGA Synthesis User Guide, February 2010
Synopsys FPGA Synthesis User Guide Copyright © 2010 Synopsys, Inc.
February 2010 5
Contents
Chapter 1: Introduction
The Synopsys FPGA Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
The FPGA Synthesis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synopsys FPGA Tool Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Scope of the Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
The Document Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Requesting Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
User Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 2: FPGA Logic Flows
Logic Synthesis Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Prototyping Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 3: Preparing the Input
Setting Up HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Creating HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Checking HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Editing HDL Source Files with the Built-in Text Editor . . . . . . . . . . . . . . . . . . . . 31
Setting Editing Window Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Using an External Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Using Mixed Language Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Working with Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
When to Use Constraint Files over Source Code . . . . . . . . . . . . . . . . . . . . . . . 42
Tcl Syntax Guidelines for Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Using a Text Editor for Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using Synopsys Design Compiler Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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