没有合适的资源?快使用搜索试试~ 我知道了~
首页altium 错误说明
altium 错误说明
需积分: 48 13 下载量 36 浏览量
更新于2023-07-07
收藏 514KB PDF 举报
This comprehensive reference describes each of the possible electrical and drafting violations that can exist in source documents when compiling a project.
资源详情
资源推荐
![](https://csdnimg.cn/release/download_crawler_static/2634165/bg1.jpg)
Project Compiler Error
Reference
Summary
Technical Reference
TR0142 (v1.1) November 03, 2007
This comprehensive reference describes each of the
possible electrical and drafting violations that can exist in
source documents when compiling a project.
The process of compiling is integral to producing a valid netlist for a project. Connectivity awareness in
your schematic diagram can be verified during compilation according to rules that are set up in your
Project Options (C » O) in the Error Reporting and Connection Matrix tabs. You can customize
reporting modes for violations in the
Error Reporting and Connection Matrix tabs. Choose from:
•
•
•
•
Figure 1. The Error Reporting tab in Project Options
To change the Report Mode for a violation in the Error Reporting tab, click on the current Report
Mode and select an alternative from the dropdown.
TR0142 (v1.1) November 03, 2007 1
![](https://csdnimg.cn/release/download_crawler_static/2634165/bg2.jpg)
TR0142 Project Compiler Error Reference
Figure 2.Selecting the Report Mode in the Error Reporting Tab
To change the Report Mode for a violation in the Connection Matrix tab, click on the existing Report
Mode to cycle through the alternatives. When you click on the Report Mode, text is displayed at the
bottom of the window to describe the connectivity violation and the Report Mode for the selection.
Figure 3.Selecting the Report Mode in the Connection Matrix Tab
Use the Set to Installation Defaults button on either the Error Reporting or Connection Matrix tabs
to reset your Reporting Modes back to their default value on installation.
Note that the Violations listed in the Error Reporting tab correspond to the compiler hints you see in
your Schematic Documents when a violation occurs.
2 TR0142 (v1.1) November 03, 2007
![](https://csdnimg.cn/release/download_crawler_static/2634165/bg3.jpg)
TR0142 Project Compiler Error Reference
To customize the visibility of compiler hints and the properties of the wavy underline for errors and
warnings:
• Select the
DXP » Preferences command which brings up the Preferences dialog
• Navigate to the
Compiler tab under the Schematic folder
• Choose to display
Fatal Errors, Errors and Warnings by enabling the Display checkbox
• If you choose to display the errors and/or warnings, a wavy underline will be displayed under your
offending object in the color specified in your preferences. You can customize the color of the wavy
underline by clicking on the respective
Color field and selecting a new color in the Choose Color
dialog
• Enable the Show Hints checkbox to display all hints in your schematic, including compiler hints
which correspond to the violations listed in the
Error Reporting tab. Run your mouse over the
offending object (denoted by a colored wavy underline) to see the compiler hints. Note that compiler
hints
are only displayed if the Display field is also enabled for each corresponding error or warning.
Figure 4.The Compiler tab in the Preferences dialog
The following sections provide the information for your compiled project including compiler hints, a
description of the message displayed in the
Messages Panel, the Default Report Mode and a
recommendation for resolution for each violation.
TR0142 (v1.1) November 03, 2007 3
![](https://csdnimg.cn/release/download_crawler_static/2634165/bg4.jpg)
TR0142 Project Compiler Error Reference
Violations Associated with Buses
Arbiter loop in OpenBus document
This compiler hint appears when the IO and MEM ports of a processor in the OpenBus System are
linked, through a single Arbiter component, to the same slave memory or I/O peripheral device,
effectively forming a loop. The message is displayed in the Messages panel in the following format:
Arbiter ArbiterName is in the loop,
where
ArbiterName is the designator of the offending Arbiter component.
Default Report Mode
Recommendation
It is nonsensical in a processor-based system to connect a slave device to both the Peripheral I/O and
External Memory interfaces of a processor concurrently. Therefore ensure that the IO and MEM ports
of a processor in the OpenBus System are linked to their intended (and different) slave devices using
distinct interconnects – Interconnect and/or Arbiter components. Typically for a single processor
system, an Interconnect component and one or more Arbiter components would be used on the MEM
side of the processor, with the processor and any memory-based peripheral I/O devices linked to slave
memory through the Arbiter(s). The IO side of the processor would involve use of an Interconnect
component only, to which the bank of peripheral I/O devices – to be used by the processor – are linked.
Bus indices out of range
This compiler hint appears when the index of a constituent net connected to a bus lies outside the
range specified by the net to which the bus is associated. The message is displayed in the
Messages
panel in the following format:
Bus index out of range on NetPrefix Index = NetIndex,
where
NetPrefix is the prefix of the constituent net connected to the bus (e.g. A for net A1, connected to a
bus associated to net A[0..7])
NetIndex is the erroneous index of the constituent net (e.g. net A8 has an index of 8).
Default Report Mode
Recommendation
Use the Compile Errors dialog to quickly cross probe to the net label associated with the offending net
and either amend the index of the net so that it lies within the correct range, or rename the net
altogether. The latter would be typical if you have named the net by mistake and it is not a constituent
of the net transported by the bus object.
4 TR0142 (v1.1) November 03, 2007
![](https://csdnimg.cn/release/download_crawler_static/2634165/bg5.jpg)
TR0142 Project Compiler Error Reference
Bus range syntax errors
This compiler hint appears when the syntax of the net to which the bus is associated is specified
incorrectly. The message is displayed in the
Messages panel in the following format:
Bus range syntax error NetName at Location,
where
NetName is the name of the parent net to which the offending bus object is associated
Location is the X, Y coordinates for the offending bus object's electrical hotspot.
Default Report Mode
Recommendation
Use the Compile Errors dialog to quickly cross probe to the offending net identifier (e.g. net label, port,
sheet entry, etc) whose bus syntax is defined incorrectly. The correct syntax should appear in one of
the following formats:
NetName[LowerIndex..UpperIndex]
NetName[UpperIndex..LowerIndex]
For example, consider a bus that carries two constituent nets, A0 and A1. The bus syntax in this case
would be
A[0..1] or A[1..0]. Examples of incorrect syntax would include:
A[0.1]
A[1-0]
A[0,1]
A[..1]
A[0..]
Cascaded Interconnects in OpenBus document
This compiler hint appears when the Master port of one Interconnect component is linked to the Slave
port of another Interconnect component, thereby forming a cascade of Interconnect components in the
OpenBus System. The message is displayed in the Messages panel in the following format:
Cascaded interconnects InterconnectName1 and InterconnectName2,
where
InterconnectName1 is the designator of the first offending Interconnect component
InterconnectName2 is the designator of the second offending Interconnect component
Default Report Mode
Recommendation
Ensure that two Interconnect components are not linked together in your OpenBus System. Typically,
there will be just two Interconnect components in a single processor system, one linked to the
TR0142 (v1.1) November 03, 2007 5
剩余53页未读,继续阅读
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://profile-avatar.csdnimg.cn/default.jpg!1)
wallin82
- 粉丝: 0
- 资源: 1
上传资源 快速赚钱
我的内容管理 收起
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助
![](https://csdnimg.cn/release/wenkucmsfe/public/img/voice.245cc511.png)
会员权益专享
最新资源
- VMP技术解析:Handle块优化与壳模板初始化
- C++ Primer 第四版更新:现代编程风格与标准库
- 计算机系统基础实验:缓冲区溢出攻击(Lab3)
- 中国结算网上业务平台:证券登记操作详解与常见问题
- FPGA驱动的五子棋博弈系统:加速与创新娱乐体验
- 多旋翼飞行器定点位置控制器设计实验
- 基于流量预测与潮汐效应的动态载频优化策略
- SQL练习:查询分析与高级操作
- 海底数据中心散热优化:从MATLAB到动态模拟
- 移动应用作业:MyDiaryBook - Google Material Design 日记APP
- Linux提权技术详解:从内核漏洞到Sudo配置错误
- 93分钟快速入门 LaTeX:从入门到实践
- 5G测试新挑战与罗德与施瓦茨解决方案
- EAS系统性能优化与故障诊断指南
- Java并发编程:JUC核心概念解析与应用
- 数据结构实验报告:基于不同存储结构的线性表和树实现
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
![](https://img-home.csdnimg.cn/images/20220527035711.png)
![](https://img-home.csdnimg.cn/images/20220527035711.png)
![](https://img-home.csdnimg.cn/images/20220527035111.png)
安全验证
文档复制为VIP权益,开通VIP直接复制
![](https://csdnimg.cn/release/wenkucmsfe/public/img/green-success.6a4acb44.png)