没有合适的资源？快使用搜索试试~ 我知道了~

首页锁相环的设计与ADS仿真资料

锁相环的设计与ADS仿真资料

频率合成

3星 · 超过75%的资源需积分: 10 33 下载量 186 浏览量更新于2023-07-10 收藏 848KB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

试读

45页

PLL Design--Analysis of a Sigma-Delta Modulator Using RF Behavioral Modeling and System Simulation

资源详情

资源推荐

PLL Design--Analysis of a Sigma-Delta Modulator

Using RF Behavioral Modeling and System Simulation

Advanced RFIC Design Techniques

Phase Locked Loop Design--

Analysis of a Sigma-Delta Modulator Using RF

Behavioral Modeling and System Simulation

by Andy Howard

Applications Engineer

Welcome to this presentation. It is designed to give you an understanding of:

• Advanced Design System (ADS) and RF Design Environment (RFDE) Phase-

locked loop (PLL) simulation capabilities.

• PLL component behavioral modeling in Agilent ADS and RFDE

• Agilent ADS and RFDE post-processing capabilities

PLL Design--Analysis of a Sigma-Delta Modulator

Using RF Behavioral Modeling and System Simulation

Page 2

Introduction

• Agilent ADS and RFDE capabilities for simulating

PLLs

• PLL component behavioral modeling

• Agilent ADS and RFDE post-processing capabilities

PLL Design--Analysis of a Sigma-Delta Modulator

Using RF Behavioral Modeling and System Simulation

Page 3

Outline

• Basic phase-locked loop (PLL) operation

• Fractional-N PLL operation and simulation

• Behavioral modeling of a phase/frequency detector

• Simulating jitter in a transistor-level PFD and charge

pump

• Behavioral modeling of a VCO/divide-by-N

• Modeling an accumulator with Ptolemy

• Sigma-delta modulators

• Simulating a PLL with a sigma-delta modulator

• Adding phase noise to the VCO

PLL Design--Analysis of a Sigma-Delta Modulator

Using RF Behavioral Modeling and System Simulation

Page 4

Basic Phase-Locked Loop

In steady-state,

VCO

=N*F

REF

This phase-locked loop consists of a reference source, phase/frequency detector,

charge pump, loop filter, VCO, and divider. If the divide ratio is a constant, then the

loop will operate to force the VCO signal frequency to be exactly N times the

reference signal frequency. The phase/frequency detector and charge pump act to

output either positive or negative charge “pulses” depending on whether the

reference signal phase leads or lags the divided VCO signal phase. These charge

pulses are integrated by the loop filter to generate a tuning voltage. The tuning

voltage forces the VCO frequency up or down, such that the reference signal and

divided signal phases are synchronized.

Phase-locked loops are used as frequency synthesizers in many applications, where it

is necessary to generate a precise signal frequency with low spurs and good phase

noise. A VCO’s signal frequency can be changed by varying the reference signal

frequency or the divide ratio. Often, the reference signal is a very stable oscillator

whose frequency cannot be varied. So the divide ratio is changed in integer steps to

change the VCO frequency.

PLL Design--Analysis of a Sigma-Delta Modulator

Using RF Behavioral Modeling and System Simulation

Page 5

Problem with Basic Phase-Locked Loop

N can only have integer values, so

VCO

=…, (N-2)* F

REF

, (N-1)* F

REF

, N* F

REF

, (N+1)* F

REF

, …

The smallest frequency change in F

VCO

that can be made is

1*F

REF

What if you need finer frequency resolution?

One limitation with this type of phase-locked loop is that the VCO frequency cannot

be varied in steps any smaller than the reference frequency. (Although you could put

a 1/M divider between the reference signal and the phase/frequency detector, in

which case the VCO output frequency would be N*Fref/M.) Due to mismatches in

the PLL’s charge pump and other factors such as the non-ideal behavior of

phase/frequency detectors, even when the loop is locked, the charge pump still

outputs small charge pulses which cause sidebands or spurs to appear in the VCO

output spectrum, at offset frequencies equal to the reference frequency. So, for fine

frequency resolution, you want a small reference frequency. But this will cause

spurs to be generated at a smaller offset frequency from the VCO, meaning they will

require that a narrower loop filter bandwidth be used to filter them. PLLs with

narrower loop bandwidths have longer transient settling times (the time required to

transition from one frequency to another) and such loops may not operate at the

required speed. Reference 1 has a discussion of PLL settling time requirements.

Also, the narrower the PLL’s loop bandwidth, the less the VCO’s phase noise is

supressed.

剩余44页未读，继续阅读

PLL_锁相环的ADS_仿真

PLL_锁相环的ADS_仿真、详细实例讲解如何用ADS进行锁相环的仿真与设计

ADS 仿真实例，适合于ADS学习的新手！

taijietou

粉丝: 0
资源: 1

上传资源快速赚钱

我的内容管理收起

我的资源快来上传第一个资源

我的收益

登录查看自己的收益

我的积分登录查看自己的积分

我的C币登录后查看C币余额

我的收藏

我的下载

下载帮助

会员权益专享

锁相环的设计与ADS仿真资料

PLL_锁相环的ADS_仿真

ADS 仿真实例，适合于ADS学习的新手！

PLL锁相环的ADS仿真

锁相环设计、仿真与应用(第5版)中文版.pdf

数字锁相环matlab仿真,锁相环仿真_MATLAB仿真程序代码_二阶锁相环仿真过程

基于dq变换的锁相环设计与仿真

锁相环并网simulink建模仿真

基于matlab的dpll设计与仿真,基于matlab的数字锁相环DPLL的仿真

锁相环simulink建模仿真.rar

锁相环fm解调电路仿真实验multisim仿真图

基于matlab的数字锁相环的仿真设计

simulink模拟锁相环仿真

matlab锁相环设计流程

锁相环相位噪声仿真matlab代码

matlab 数字锁相环仿真

cd4046锁相环proteus仿真.rar

锁相环滑模观测器matlab仿真

cd4046锁相环电路仿真

三相锁相环仿真matlab

sogi锁相环simulink仿真

会员权益专享

最新资源