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Table of Contents Virtuoso-XL Layout Editor
December 16, 2002 Cadence Design Systems, Inc. iii
Table of Contents
Virtuoso-XL Layout Editor
Module 1 Introduction to VXL
Course Outline and Schedule........................................................................................... 1-3
Virtuoso-XL Environment...............................................................................................1-5
What Is Virtuoso-XL?...................................................................................................... 1-7
What Is Virtuoso Custom Placer?.................................................................................... 1-9
What Is the Cadence Chip Assembly Router?............................................................... 1-11
Cadence Online Documentation System ....................................................................... 1-13
Labs................................................................................................................................ 1-15
Module 2 Virtuoso-XL Setup
Technology File Overview .............................................................................................. 2-3
lxRules Class–Extract Layers.......................................................................................... 2-5
Layer Rules Class ............................................................................................................ 2-7
Devices Class...................................................................................................................2-9
Physical Rules Class ...................................................................................................... 2-11
lxRules Class–No Overlap Layers ................................................................................ 2-13
Placing Design Elements Using Layout Generation...................................................... 2-15
Setting Up Properties..................................................................................................... 2-17
Parameters and Properties.............................................................................................. 2-19
One-to-Many Mapping in Schematic............................................................................. 2-21
Series Connection Factor............................................................................................... 2-23
Specifying Which Layout to Use................................................................................... 2-25
Using Layout from a Different Cell or Library ............................................................. 2-27
CDF Requirements......................................................................................................... 2-29
Ignore Devices in Layout Generation............................................................................2-31
lxRemoveDevice Property.............................................................................................2-33
Preparing Pins for Virtuoso-XL..................................................................................... 2-35
Preparing Pins for Permutability.................................................................................... 2-37
Device Abutment ........................................................................................................... 2-39
Device Abutment Parameters ........................................................................................ 2-41
Device Abut and Stretch Parameters ............................................................................. 2-43
Setting Up Your Desktop............................................................................................... 2-45
Changing Display Colors............................................................................................... 2-47
Bindkeys for Virtuoso-XL............................................................................................. 2-49
Setting Virtuoso-XL Environment Variables ................................................................ 2-51
Labs................................................................................................................................ 2-53
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Virtuoso-XL Layout Editor Table of Contents
iv Cadence Design Systems, Inc. December 16, 2002
Module 3 Layout Generation
Schematic Connectivity Reference..................................................................................3-3
Netlist Connectivity Reference........................................................................................3-5
Importing a Netlist Flow.................................................................................................. 3-7
Importing a Netlist........................................................................................................... 3-9
Mapping File Example................................................................................................... 3-11
Defining a Connectivity Reference................................................................................ 3-13
Initial Placement–Schematics ....................................................................................... 3-15
Initial Placement–Netlists ............................................................................................. 3-17
Layout Generation Form–Top....................................................................................... 3-19
Layout Generation Form–Bottom................................................................................. 3-21
Placing Components Automatically .............................................................................. 3-23
Picking from the Schematic...........................................................................................3-25
Cloning........................................................................................................................... 3-27
Cloning Source and Target ............................................................................................ 3-29
Cloning Form.................................................................................................................3-31
Creating Device Correspondence .................................................................................. 3-33
Labs................................................................................................................................ 3-35
Module 4 Editing Virtuoso-XL Placement
Exploring Connectivity.................................................................................................... 4-3
Moving Components Manually ....................................................................................... 4-5
Aligning Objects.............................................................................................................. 4-7
Swapping Components .................................................................................................... 4-9
Permuting Pins...............................................................................................................4-11
Device Abutment ........................................................................................................... 4-13
Transistor Chaining........................................................................................................ 4-15
Transistor Folding.......................................................................................................... 4-17
Probing Devices.............................................................................................................4-19
Probing–List Nets..........................................................................................................4-21
Labs................................................................................................................................ 4-23
Module 5 Creating Interconnect in Virtuoso-XL
Understanding Connectivity ............................................................................................ 5-3
Connectivity Extractor.....................................................................................................5-5
Creating Interconnect....................................................................................................... 5-7
Creating Interconnect with Paths.....................................................................................5-9
Permuting Pins...............................................................................................................5-11
Adding External Connections to Devices......................................................................5-13
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Table of Contents Virtuoso-XL Layout Editor
December 16, 2002 Cadence Design Systems, Inc. v
Creating Paths with Path Stitching ................................................................................ 5-15
Maintaining Connections...............................................................................................5-17
Highlighting Components and Nets............................................................................... 5-19
Checking Connectivity with Markers............................................................................ 5-21
Verifying Shorts and Opens........................................................................................... 5-23
Optimizing Virtuoso-XL Performance .......................................................................... 5-25
Labs................................................................................................................................ 5-27
Module 6 Wire Editor
Wire Editor Features........................................................................................................6-3
Wire Editor Environment................................................................................................. 6-5
Enabling the Wire Editor ................................................................................................. 6-7
Wire Editor Options......................................................................................................... 6-9
Via Assistance................................................................................................................ 6-11
Orthogonal Jogs ............................................................................................................. 6-13
Show Timing Length/Rule............................................................................................. 6-15
Route to Cursor..............................................................................................................6-17
Options–Other............................................................................................................... 6-19
WE Options.................................................................................................................... 6-21
WE Shielding.................................................................................................................6-23
Rules .............................................................................................................................. 6-25
Bus Routing ................................................................................................................... 6-27
Bus Routing Options...................................................................................................... 6-29
Bus Routing Vias and Dropped Wires........................................................................... 6-31
Setting Constraints.........................................................................................................6-33
Wire Editing Environment Variables............................................................................. 6-35
Creating Paths................................................................................................................ 6-37
Creating Interconnect..................................................................................................... 6-39
Path Stitching Gate Connections ................................................................................... 6-41
Split Paths to Add Vertices............................................................................................6-43
Stretch ............................................................................................................................ 6-45
Pull................................................................................................................................. 6-47
Copy Route .................................................................................................................... 6-49
Critic Wire ..................................................................................................................... 6-51
Check Route................................................................................................................... 6-53
Verify Report ................................................................................................................. 6-55
Installation, Licensing, and Setup.................................................................................. 6-57
Labs................................................................................................................................ 6-59
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