TI DSP源码解析与配置指南

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"该资源包含了与DSP相关的资料，特别是与TI产品有关的源代码和PDF文档。提供的代码示例展示了如何配置ADC（模数转换器）的寄存器以进行正确的设置和操作。" 在这些代码片段中，我们看到的是针对某种特定的DSP处理器（可能是基于DSP5402的系统）进行ADC配置的过程。以下是一些关键知识点： 1. **ADC控制寄存器配置**：ADC的操作是通过设置一系列控制寄存器来完成的。例如，`AdcRegs.ADCTRL1` 和 `AdcRegs.ADCTRL3` 被用于设定ADC的工作模式、采样保持时间、时钟分频器等参数。 2. **复位和模式选择**：`AdcRegs.ADCTRL1.bit.RESET` 用于对ADC进行复位，而`AdcRegs.ADCTRL1.bit.SUSMOD` 设置采样模式，`AdcRegs.ADCTRL1.bit.ACQ_PS` 控制采样时间，`AdcRegs.ADCTRL1.bit.CONT_RUN` 决定ADC是否连续运行，`AdcRegs.ADCTRL1.bit.SEQ_CASC` 用于序列级联。 3. **电源管理**：`AdcRegs.ADCTRL3.bit.ADCPWDN` 控制ADC的电源，`AdcRegs.ADCTRL3.bit.ADCCLKPS` 设定ADC时钟预分频器，`AdcRegs.ADCTRL3.bit.SMODE_SEL` 选择工作模式。 4. **最大转换次数设置**：`AdcRegs.MAX_CONV.bit.MAX_CONV` 设置最大连续转换次数。 5. **通道选择**：ADC的通道选择由 `AdcRegs.CHSELSEQ1` 至 `AdcRegs.CHSELSEQ4` 寄存器定义，这些寄存器用于指定ADC将依次转换哪些通道。 6. **中断和序列标志**：`AdcRegs.ADC_ST_FLAG` 寄存器中的 `INT_SEQ1_CLR` 和 `INT_SEQ2_CLR` 用于清除中断状态标志，而 `AdcRegs.ADCTRL2` 中的相关位则用于设置中断使能和序列操作。 7. **EVB和SOC序列控制**：`AdcRegs.ADCTRL2` 的其他位涉及到扩展电压基准（EVB）、系统时钟输出（SOC）以及中断模式的配置。 8. **延时循环**：代码中用到的 `NOP` 指令是无操作指令，通常用来插入延迟周期，确保操作按预期顺序执行。 9. **TI DSP5402特性**：虽然没有直接提供TI DSP5402的详细资料，但根据标签，我们可以推断这是针对该型号的处理器进行的编程。DSP5402是一款古老的数字信号处理器，具有高级多总线架构，支持16位数据总线，包括40位ALU、独立的乘法器和累加器，适用于高速计算任务，如Viterbi算法操作和非流水线MAC运算。 10. **片上存储**：该处理器有4Kx16位的片上ROM和16Kx16位的双访问片上RAM，以及支持扩展地址模式以便访问更大的外部程序空间。这些代码片段和文档可能对于理解如何在实际应用中配置和控制TI DSP5402的ADC非常有帮助，同时也揭示了经典DSP处理器的一些核心功能和编程模式。

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   

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory

The 5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

The 5402 features a 4K-word

× 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the

5402 programmed with contents unique to any particular application. A security option is available to protect

a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals Reference Set,

Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,

is available on the 5402 .

A bootloader is available in the standard 5402 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC

is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location

contains a branch instruction to the start of the bootloader program. The standard 5402 bootloader provides

different ways to download the code to accomodate various system requirements:

D Parallel from 8-bit or 16-bit-wide EPROM

D Parallel from I/O space 8-bit or 16-bit mode

D Serial boot from serial ports 8-bit or 16-bit mode

D Host-port interface boot

The standard on-chip ROM layout is shown in Table 1.

Table 1. Standard On-Chip ROM Layout

†

ADDRESS RANGE DESCRIPTION

F000h − F7FFh Reserved

F800h − FBFFh Bootloader

FC00h − FCFFh µ-law expansion table

FD00h − FDFFh A-law expansion table

FE00h − FEFFh Sine look-up table

FF00h − FF7Fh Reserved

FF80h − FFFFh Interrupt vector table

†

In the ’VC5402 ROM, 128 words are reserved for factory device-testing purposes. Application

code to be implemented in on-chip ROM must reserve these 128 words at addresses

FF00h–FF7Fh in program space.

on-chip RAM

The 5402 device contains 16K

× 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of two

blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write

in one cycle. The DARAM is located in the address range 0060h−3FFFh in data space, and can be mapped

into program/data space by setting the OVLY bit to one.



   

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC

= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F

0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Interrupts

(External)

FF80

Memory

Mapped

Registers

On-Chip DARAM

(16K x 16-bit)

ROM (DROM=1)

or External

(DROM=0)

0080

FFFF

Hex

0000

FF7F

FF00

FEFF

EFFF

F000

FFFF

3FFF

4000

0060

007F

0000

Hex

Page 0 Program

External

Scratch-Pad

RAM

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F

0080

3FFF

4000

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

FF00

FEFF

EFFF

F000

External

On-Chip ROM

(4K x 16-bit)

Interrupts

(On-Chip)

3FFF

4000

Reserved

FF7F

FF80

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch

instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate

interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,

these vectors can be remapped to the beginning of any 128-word page in program space after device reset.

This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the

appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped

to the new 128-word page.

NOTE: The hardware reset (RS

) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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