微芯片93LC56BTISNSPIEEPROM技术规格
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"该文档是关于Microchip Technology Inc.的93LC56BTISNSPI EEPROM的详细技术资料，特别适用于单片机/嵌入式系统，特别是STM32-F0/F1/F2系列。这份资料介绍了93AA56A/B/C, 93LC56A/B/C, 和93C56A/B/C设备的主要特性和功能，以及它们在不同应用场景中的应用。"
93LC56BTISNSPI EEPROM是Microchip Technology Inc.推出的一种2Kbit低电压串行电可擦除存储器，具有多种版本以适应不同的数据组织需求。此系列器件的主要特点包括：
1. 低功耗CMOS技术：这些设备使用了节能的CMOS工艺，适合于电池供电或对能耗有严格要求的系统。
2. ORG引脚：对于93LC56C、93C56C等具有词选功能的版本，可以通过外部逻辑电平驱动ORG引脚来选择词的大小。8位通信可以选择93XX56A设备，而16位通信则可以选择93XX56B设备。
3. 自动操作：支持自定时的擦除/写入周期，包括自动擦除功能。在写入前，会自动执行ERAL（擦除前读取）以确保数据安全。
4. 数据保护：电源开启和关闭时，内建的数据保护电路确保数据安全。
5. 三线串行I/O接口：遵循工业标准的三线串行接口，提供Ready/Busy设备状态信号，用于监控设备是否忙于处理操作。
6. 序列读取功能：允许连续读取数据，提高数据传输效率。
7. 高耐久性：1,000,000次擦写循环，确保了设备的长期可靠性。
8. 长期数据保留：数据保留时间超过200年，满足长期存储的需求。
9. 环保合规：无铅且符合RoHS标准，满足环保要求。
10. 温度范围：支持多种温度范围，以适应不同环境条件下的应用。
93LC56BTISNSPI EEPROM因其低功耗、高耐久性和灵活的数据组织方式，非常适合在嵌入式系统，特别是STM32-F0/F1/F2单片机中使用，作为非易失性存储解决方案，用于存储配置参数、固件更新或其他关键数据。开发者可以依据其项目需求，选择合适的设备版本以优化性能和成本。
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
DS21794E-page 6 © 2007 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
When the ORG pin (93XX56C) pin is connected to
V
CC, the (x16) organization is selected. When it is
connected to ground, the (x8) organization is selected.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a High-Z state except when read-
ing data from the device, or when checking the Ready/
Busy
status during a programming operation. The
Ready/Busy
status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1 START Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3 Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
Note: When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
Note: For added protection, an EWDS command
should be performed after every write
operation and an external 10 kΩ pull-down
protection resistor should be added to the
CS pin.
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
V
CC VSS
*ORG input is not available on A/B devices
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