SATA 2.5 Gold标准：接口状态与设备初始化详解

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SATA (Serial Advanced Technology Attachment) 是一种串行接口标准，用于在计算机内部连接硬盘驱动器等存储设备。SATA__2.5_Gold 版本是在 SATA 2.5规范基础上的增强版，它提供更快的数据传输速度、更高级别的错误检测和处理机制以及更优化的设备管理功能。在这个规范文档中，主要关注的是 SATA 接口的不同状态（Interface Power States 和 Device Phy Initialization States）和链接层状态（Link Layer States），这些状态对于理解和操作 SATA 设备至关重要。以下是各部分的详细说明： 1. **Interface Power States**: - HR_AdjustSpeed: 该状态用于调整数据传输速率，可能涉及到兼容性调整或性能优化。 - HR_AwaitAlign: 设备等待数据传输前的正确对齐操作，以确保数据的正确读写。 - HR_AwaitCOMINIT/HR_AwaitNoCOMINIT/HR_AwaitCOMWAKE/HR_AwaitNoCOMWAKE: 这些状态涉及通信初始化和唤醒过程，确保设备间的通信有效。 - HR_Calibrate: 数据校准阶段，确保信号的准确无误。 - HR_COMWAKE: 从低功耗模式唤醒到活动状态。 - HR_Partial: 发生部分数据传输时的状态。 - HR_Ready: 设备准备接收或发送数据。 - HR_Reset: 设备复位，恢复到初始状态。 - HR_SendAlign: 发送数据对齐信号。 - HR_Slumber: 低功耗状态，类似于休眠，但比 DR_Slumber 更高效。 2. **Device Phy Initialization States**: - DR_AwaitCOMWAKE/DR_AwaitNoCOMWAKE: 设备等待与接口通信的唤醒或非唤醒状态。 - DR_Calibrate: 初始化过程中进行数据校准。 - DR_COMINIT: 开始设备通信初始化。 - DR_COMWAKE: 设备从低功耗状态恢复通信。 - DR_Error: 发生错误时的状态。 - DR_Partial: 发生部分数据处理。 - DR_Ready: 设备准备好执行命令。 - DR_ReduceSpeed: 减速传输，可能用于降低能耗。 - DR_Reset: 设备重置。 - DR_SendAlign: 发送数据对齐信号。 - DR_Slumber: 低功耗状态，类似 HR_Slumber。 3. **Link Layer States**: - L_SyncEscape: 发生同步逃逸时的状态，用于恢复同步。 - L_IDLE: 没有正在进行的通信。 - L_NoComm/L_NoCommErr: 无通信或通信错误的状态。 - L_RESET: 接收到硬件或软件复位命令时的状态。 - L_SendAlign: 发送数据对齐信息。 - L_RcvrHold: 接收端保持接收缓冲区的稳定。 - L_SendCRC/L_SendDat: 发送数据包时的状态，包括校验码和实际数据。这些状态在系统管理和故障诊断中扮演着关键角色，有助于确保 SATA 设备的正常运行和高效性能。理解并掌握这些状态变化对于正确配置和监控 SATA 系统，优化存储性能以及在遇到问题时快速定位和解决都极为重要。

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16.3.1

Addressing Mechanism ....................................................................................... 504

16.3.2 Device Port Requirements................................................................................... 504

16.3.3 Policies................................................................................................................. 506

16.4 Port Multiplier Registers .............................................................................................. 516

16.4.1 General Status and Control Registers................................................................. 516

16.4.2 Port Status and Control Registers ....................................................................... 525

16.5 Port Multiplier Command Definitions ........................................................................... 526

16.5.1 READ PORT MULTIPLIER.................................................................................. 526

16.5.2 WRITE PORT MULTIPLIER................................................................................ 528

16.5.3 Interrupts.............................................................................................................. 530

16.6 Controlling PM Port value and Interface Power Management .................................... 530

16.7 Switching Types (Informative) ..................................................................................... 530

16.7.1 Command-based switching ................................................................................. 530

16.7.2 FIS-based switching ............................................................................................ 530

17 Port Selector .................................................................................................................... 532

17.1 Example Applications .................................................................................................. 532

17.2 Overview ...................................................................................................................... 533

17.3 Active Port Selection.................................................................................................... 534

17.3.1 Protocol-based Port Selection ............................................................................. 534

17.3.2 Side-band Port Selection ..................................................................................... 537

17.3.3 Behavior during a change of active port .............................................................. 537

17.4 Behavior and Policies .................................................................................................. 538

17.4.1 Control State Machine ......................................................................................... 538

17.4.2 BIST support ........................................................................................................ 542

17.4.3 Flow control signaling latency.............................................................................. 542

17.4.4 Power Management............................................................................................. 542

17.4.5 OOB Phy signals ................................................................................................. 543

17.4.6 Hot Plug ............................................................................................................... 543

17.4.7 Speed Negotiation ............................................................................................... 543

17.4.8 Spread spectrum clocking ................................................................................... 544

17.5 Power-up and Resets .................................................................................................. 544

17.5.1 Power-up ............................................................................................................. 544

17.5.2 Resets.................................................................................................................. 544

17.6 Host Implementation (Informative) .............................................................................. 544

17.6.1 Software Method for Protocol-based Selection (Informative).............................. 544

Appendix A. Sample Code for CRC and Scrambling (Informative) ......................................... 547

A.1 CRC calculation ........................................................................................................... 547

A.1.1 Overview .............................................................................................................. 547

A.1.2 Maximum frame size............................................................................................ 547

A.1.3 Example code for CRC algorithm ........................................................................ 547

A.1.4 Example code for CRC algorithm ........................................................................ 547

A.1.5 Example CRC implementation output ................................................................. 549

A.2 Scrambling calculation................................................................................................. 550

A.2.1 Overview .............................................................................................................. 550

A.2.2 Example code for scrambling algorithm .............................................................. 550

A.2.3 Example scrambler implementation .................................................................... 550

A.2.4 Example scrambler implementation output ......................................................... 553

A.3 Example frame............................................................................................................. 554

Appendix B. Command processing overview (Informative) ..................................................... 555

B.1 Non-data commands ................................................................................................... 555

B.2 DMA read by host from device .................................................................................... 555

B.3 DMA write by host to device ........................................................................................ 555

B.4 PIO data read from the device..................................................................................... 556

B.5 PIO data write to the device ........................................................................................ 556

B.6 ATA Tagged Command Queuing DMA read from device ........................................... 557

B.7 ATA Tagged Command Queuing DMA write to device ............................................... 558

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B.8

ATAPI Packet commands with PIO data in ................................................................. 558

B.9 ATAPI Packet commands with PIO data out............................................................... 559

B.10 ATAPI Packet commands with DMA data in ............................................................... 560

B.11 ATAPI Packet commands with DMA data out ............................................................. 561

B.12 Odd word count considerations ................................................................................... 562

B.12.1 DMA read from target for odd word count ........................................................... 563

B.12.2 DMA write by host to target for odd word count .................................................. 563

B.13 PIO data read from the device..................................................................................... 563

B.14 PIO data write to the device ........................................................................................ 564

B.15 Native Command Queuing Examples (Informative) .................................................... 564

B.15.1 Queued Commands with Out of Order Completion............................................. 564

B.15.2 Interrupt Aggregation ........................................................................................... 566

Appendix C. Device Emulation of nIEN with Interrupt Pending (Informative) ...................... 569

Appendix D. I/O Controller Module (Informative) ................................................................. 570

D.1 Supported Configurations ............................................................................................ 570

D.1.1 Single I/O Controller Signals ............................................................................... 571

D.1.2 Dual I/O Controller Signals .................................................................................. 572

D.1.3 Further optional features...................................................................................... 572

D.2 Optional High Speed Channel configurations ............................................................. 573

D.3 Optional Low Speed Channel configurations .............................................................. 575

D.4 I/O Controller Module Connectors ............................................................................... 576

D.4.1 I/O Controller Module Connector......................................................................... 576

D.5 I/O Controller Module Connector Locations ................................................................ 579

D.5.1 Purpose................................................................................................................ 579

D.6 Pinout Listing ............................................................................................................... 582

D.7 Signal Descriptions ...................................................................................................... 583

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TABLE OF FIGURES

Figure 1 – Byte, word and Dword relationships............................................................................. 37

Figure 2 – Parallel ATA device connectivity .................................................................................. 38

Figure 3 – Serial ATA connectivity ................................................................................................ 39

Figure 4 – Communication layers.................................................................................................. 40

Figure 5 – Internal 1 meter Cabled Host to Device Application .................................................... 41

Figure 6 – Short Backplane to Device Application ........................................................................ 42

Figure 7 – Long Backplane to Device Application......................................................................... 43

Figure 8 – Internal 4-lane Cabled Disk Array ................................................................................ 44

Figure 9 – System to System Interconnects.................................................................................. 45

Figure 10 – External Desktop Application ..................................................................................... 46

Figure 11 – SATA Disk Arrays....................................................................................................... 47

Figure 12 – Enclosure example using Port Multipliers with Serial ATA as the connection within the

rack ........................................................................................................................................ 49

Figure 13 – Enclosure example using Port Multipliers with a different connection within the rack50

Figure 14 – Mobile docking station example using a Port Multiplier ............................................. 51

Figure 15 – Serial ATA connector examples................................................................................. 53

Figure 16 – SATA Cable / Connector Connection Diagram .......................................................... 54

Figure 17 – SATA Host / Device Connection Diagram.................................................................. 55

Figure 18 – Optical Device Plug Connector Location on 5.25" form factor................................... 56

Figure 19 – Non-Optical Alternate Device Plug Connector Location on 5.25" form factor ........... 57

Figure 20 – Device Plug Connector Location on 3.5” Side Mounted Device ................................ 58

Figure 21 – Device Plug Connector Location on 3.5" Bottom Mounted Device............................ 59

Figure 22 – Device Plug Connector Location on 2.5” Side Mounted Device ................................ 60

Figure 23 – Device Plug Connector Location on 2.5" Bottom Mounted Device............................ 61

Figure 24 – Device Plug Connector Location on 1.8" Side Mounted Device ................................ 62

Figure 25 – Device Plug Connector Location on 1.8" Bottom Mounted Device............................ 63

Figure 26 – Device Plug Connector Keep Out Zones ................................................................... 64

Figure 27 – Device Plug Connector............................................................................................... 65

Figure 28 – Device Plug Connector (additional views).................................................................. 66

Figure 29 – Connector Pin and Feature Locations........................................................................ 68

Figure 30 – Cable receptacle connector interface dimensions ..................................................... 69

Figure 31 – Latching signal cable receptacle ................................................................................ 70

Figure 32 – Host signal plug connector interface dimensions....................................................... 71

Figure 33 – Non-Latching Connector Stack Spacing and Orientation .......................................... 72

Figure 34 – Latching Connector Stack Spacing and Orientation .................................................. 72

Figure 35 – Backplane connector interface dimensions................................................................ 74

Figure 36 – Connector pair blind-mate misalignment tolerance.................................................... 75

Figure 37 – Device-backplane mating configuration ..................................................................... 76

Figure 38 – Power receptacle connector interface dimensions .................................................... 77

Figure 39 – Latching power cable receptacle................................................................................ 78

Figure 40 – Detailed cross-section of an example internal single lane cable ............................... 79

Figure 41 – Isometric drawings of the internal 2 Lane cable and connector................................. 84

Figure 42 – Isometric drawings of the internal 4 Lane cable and connector................................. 85

Figure 43 – 4 Lane Pin Assignments............................................................................................. 86

Figure 44 – 4 Lane to 4 x 1 Lanes, Fanout Implementation.......................................................... 87

Figure 45 – 4 Lane Fanout Pin Assignments ................................................................................ 88

Figure 46 – 2 Lane Fanout Pin Assignments ................................................................................ 89

Figure 47 – Usage Model for HBA with external cable and single device enclosure.................... 90

Figure 48 – Usage Model for on-Board Serial ATA Connector with extension cable to external

cable to disk........................................................................................................................... 91

Figure 49 – Renderings of External Serial ATA cable receptacle and right angle plug ................ 92

Figure 50 – Mechanical dimensions of External Serial ATA cable receptacle assembly.............. 93

Figure 51 – Mechanical dimensions of External Serial ATA RA SMT plug................................... 94

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Figure 52 – Mechanical dimensions of External SATA RA SMT plug – Reversed Pin Out .......... 95

Figure 53 – Mechanical dimensions of External Serial ATA RA Through-hole............................. 96

Figure 54 – Mechanical dimensions of External Serial ATA Vertical SMT plug............................ 97

Figure 55 – Mechanical dimensions of External Serial ATA Vertical Through-hole plug.............. 98

Figure 56 –External Multi Lane cable and connector .................................................................. 100

Figure 57 – Multi Lane Cable Connector Blocking Key Locations .............................................. 101

Figure 58 – Plug/Receptacle Keying ........................................................................................... 102

Figure 59 – Example activity signal electrical block diagram ...................................................... 113

Figure 60 – Example host LED driver circuits ............................................................................. 114

Figure 61 – Example host circuit for signaling staggered spin-up disable .................................. 116

Figure 62 – Typical precharge configuration ............................................................................... 117

Figure 63 – Example presence detection implementation .......................................................... 118

Figure 64 – Physical plant overall block diagram (Informative)................................................... 122

Figure 65 – Analog front end (AFE) block diagram ..................................................................... 125

Figure 66 – Analog front end (AFE) cabling ................................................................................ 127

Figure 67 – The Simplex Link...................................................................................................... 128

Figure 68 – Common mode biasing examples for Gen1i (Informative)....................................... 142

Figure 69 – Common mode biasing for Gen1x, Gen2i, and Gen2x ............................................ 143

Figure 70 – Differential Return Loss Limits ................................................................................. 145

Figure 71 – Common Mode Return Loss Limits.......................................................................... 146

Figure 72 – Impedance Balance Limits ....................................................................................... 147

Figure 73 – Signal rise and fall times .......................................................................................... 148

Figure 74 – TX Intra-pair Skew.................................................................................................... 149

Figure 75 – OOB Differential Delta (at Compliance Point with AC coupling) .............................. 150

Figure 76 – LL Laboratory Load .................................................................................................. 152

Figure 77 – LSS Lab-Sourced Signal.......................................................................................... 153

Figure 78 – RX Differential Input Voltage Conditions.................................................................. 153

Figure 79 – RX Intra-pair Skew ................................................................................................... 155

Figure 80 – Far-End Retimed Loopback ..................................................................................... 158

Figure 81 – Far-End Analog Loopback ....................................................................................... 158

Figure 82 – Near-End Analog Loopback ..................................................................................... 159

Figure 83 – Compliant test patterns ............................................................................................ 161

Figure 84 – Low Transition Density Pattern (LTDP) starting with RD-........................................ 163

Figure 85 – Low Transition Density Pattern (LTDP) starting with RD+....................................... 164

Figure 86 – High Transition Density Pattern (HTDP) starting with RD–...................................... 165

Figure 87 – High Transition Density Pattern (HTDP) starting with RD+ ..................................... 166

Figure 88 – Low Frequency Spectral Content Pattern (LFSCP) starting with RD– .................... 167

Figure 89 – Low Frequency Spectral Content Pattern (LFSCP) starting with RD+ .................... 168

Figure 90 – Simultaneous Switching Outputs Pattern (SSOP) starting with RD–....................... 169

Figure 91 – Simultaneous Switching Outputs Pattern (SSOP) starting with RD+....................... 169

Figure 92 – Lone-Bit Pattern (LBP) starting with RD–................................................................. 170

Figure 93 – Lone-Bit Pattern (LBP) starting with RD+ ................................................................ 170

Figure 94 – Composite-Bit Pattern (COMP) starting with RD- .................................................... 173

Figure 95 – Composite-Bit Pattern (COMP) starting with RD+ ................................................... 176

Figure 96 – Example Circuit for Common Mode Transients ....................................................... 178

Figure 97 – Mated Connector Pair .............................................................................................. 179

Figure 98 – Mated Connector Pair, Pin Tail Detail ...................................................................... 180

Figure 99 – Compliance Channel Loss for Gen2x ...................................................................... 182

Figure 100 – Compliance Channel Loss for Gen1x .................................................................... 183

Figure 101 – SSC Profile Example: Triangular ........................................................................... 187

Figure 102 – Spectral fundamental frequency comparison......................................................... 188

Figure 103 – Jitter Deviations...................................................................................................... 189

Figure 104 – Edge to Edge Timing.............................................................................................. 190

Figure 105 – Differential Voltage Amplitude Measurement......................................................... 195

Figure 106 – Differential Voltage Amplitude Measurement Pattern Example............................. 195

Figure 107 – LFTP Pattern on High BW Scope (HBWS) ............................................................ 203

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Figure 108 – Single Ended Rise and Fall Time........................................................................... 206

Figure 109 – Transmit Amplitude Test with Laboratory Load ..................................................... 207

Figure 110 – Transmit Amplitude Test with Compliance Interconnect Channel ......................... 207

Figure 111 – Receiver Amplitude Test--Setting Levels ............................................................... 209

Figure 112 – Receiver Amplitude Test ........................................................................................ 209

Figure 113 - Voltage at Receiver Input........................................................................................ 210

Figure 114 – TX Long Term Frequency Measurement ............................................................... 213

Figure 115 – Receiver Model for Jitter ........................................................................................ 214

Figure 116 – Jitter at Receiver .................................................................................................... 215

Figure 117 – Jitter at Receiver, High Pass Function ................................................................... 215

Figure 118 – Transmitter Jitter Test (Gen1i, Gen2i).................................................................... 217

Figure 119 – Transmit Jitter Test with Compliance Interconnect Channel (Gen1x, Gen2x)....... 217

Figure 120 – Receiver Jitter and CM Tolerance Test--Setting Levels ........................................ 218

Figure 121 – Receiver Jitter and CM Tolerance Test.................................................................. 219

Figure 122 – Return Loss Test--Calibration ................................................................................ 221

Figure 123 – Return Loss Test .................................................................................................... 222

Figure 124 – Intra-pair Skew test for a transmitter ...................................................................... 224

Figure 125 – Receiver Intra-pair Skew Test-Setting Levels........................................................ 224

Figure 126 – Receiver Intra-pair Skew Test................................................................................ 225

Figure 127 – Example Intra-pair Skew test for Transmitter (10.8 pS)......................................... 225

Figure 128 – TX/RX Sequencing Transient Voltage Measurement ............................................ 226

Figure 129 – AC Coupled Capacitance Measurement................................................................ 227

Figure 130 – Squelch Detector Threshold Test--Setting Levels ................................................. 230

Figure 131 – Squelch Detector Threshold Test........................................................................... 230

Figure 132 – TDR Impedance Test--Setting Risetime ................................................................ 232

Figure 133 – TDR Impedance Test ............................................................................................. 232

Figure 134 – TDR Impedance Test--Setting Risetime ................................................................ 233

Figure 135 – DC Coupled Common Mode Voltage Measurement.............................................. 234

Figure 136 – AC Coupled Common Mode Voltage Measurement.............................................. 235

Figure 137 – TDR Impedance Test ............................................................................................. 235

Figure 138 – OOB signals ........................................................................................................... 237

Figure 139 – Transmitter examples............................................................................................. 238

Figure 140 – Transmitter examples (concluded)......................................................................... 239

Figure 141 – COMRESET sequence .......................................................................................... 240

Figure 142 – COMINIT sequence................................................................................................ 242

Figure 143 – OOB signal detector ............................................................................................... 245

Figure 144 – Squelch detector .................................................................................................... 246

Figure 145 – Power-on Sequence............................................................................................... 258

Figure 146 – PHYRDY to Partial/Slumber - Host initiated .......................................................... 261

Figure 147 – PHYRDY to Partial/Slumber - device initiated ....................................................... 262

Figure 148 – Bit designations ...................................................................................................... 265

Figure 149 – Nomenclature reference......................................................................................... 266

Figure 150 – Conversion examples............................................................................................. 266

Figure 151 – Encoding examples ................................................................................................ 270

Figure 152 – Bit ordering and significance .................................................................................. 276

Figure 153 – Single bit error with two character delay ................................................................ 278

Figure 154 – Single bit error with one character delay................................................................ 278

Figure 155 – Transmission structures ......................................................................................... 279

Figure 156 – CONT

usage example .......................................................................................... 285

Figure 157 – FIS type value assignments ................................................................................... 319

Figure 158 – Register - Host to Device FIS layout ...................................................................... 320

Figure 159 – Register - Device to Host FIS layout ...................................................................... 322

Figure 160 – Set Device Bit - Device to Host FIS layout............................................................. 324

Figure 161 – DMA Activate - Device to Host FIS layout.............................................................. 326

Figure 162 – DMA Setup – Device to Host or Host to Device FIS layout ................................... 327

Figure 163 – BIST Activate - Bidirectional................................................................................... 330

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