FASM 1.73 汇编器程序员手册

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"FASM 1.73 Programmer's Manual 是一本针对Flat Assembler 1.73的程序员手册，由Tomasz Grysztar编写。这份文档是随FASM源码包一同发布的，主要面向汇编语言程序员，特别是新手，提供了开始使用FASM所需的关键信息。" 在深入讲解FASM之前，首先需要了解汇编语言的基础。汇编语言是一种低级编程语言，它与机器代码紧密相关，每条指令都对应着处理器可以直接执行的特定操作。FASM，全称Flat Assembler，是一个快速的x86架构处理器汇编器，它能进行多轮优化以减小生成的机器代码大小。FASM是自编译的，即它可以编译自身，并且为不同的操作系统提供版本，包括Windows、Linux等。 1.1 编译器概述 FASM的特点在于它的高效和优化能力。它不仅将源代码转换成机器代码，还通过多次遍历来优化输出，以实现更小的二进制文件。FASM有两种主要形式：命令行版本（fasm.exe）和集成开发环境（IDE）版本（fasmw.exe）。尽管IDE版本提供了图形界面和内置编辑器，但从编译的角度看，两者功能相同。 1.1.1 系统要求使用FASM时，需要满足一定的系统要求。尽管具体要求未在摘要中详细说明，通常FASM应能在支持x86或x64架构的大多数现代操作系统上运行，包括Windows、Linux和DOS等。这可能需要具备兼容的CPU、足够的内存以及对操作系统级别的命令行或图形界面的支持。 1.2 FASM语法与指令 FASM支持一种高级的汇编语法，使得代码更加简洁易读。它允许使用符号、宏和其他高级特性，如模块化编程，使得大型项目管理变得容易。FASM的语法通常比传统的汇编语言更加直观，减少了繁琐的后缀和前缀。 1.3 使用FASM进行编程开始使用FASM时，你需要了解如何编写源代码文件，如何定义段、变量和函数，以及如何调用系统调用。FASM的命令行版本需要用户熟悉DOS或Unix风格的命令行操作，如指定输入文件和输出文件，以及任何额外的编译选项。 1.4 宏和模块 FASM的宏系统是其强大之处之一，它允许程序员创建可重用的代码块，这些代码块可以在多个地方重复使用，从而提高效率和代码一致性。模块化编程则让大型程序的组织更加有序，每个模块可以独立编译和测试。 1.5 错误处理和调试 FASM在编译期间会捕获并报告错误，帮助程序员定位和修复问题。对于调试，虽然FASM本身不提供内置的调试工具，但可以与其他调试器（如OllyDbg或GDB）配合使用，以调试由FASM编译的程序。 1.6 输出和链接 FASM产生的输出通常是可链接的目标文件，可以使用链接器（如Microsoft的LINK或GNU的ld）进一步处理，生成可执行文件。此外，FASM也可以直接生成可执行文件，取决于编译选项。总结来说，FASM 1.73程序员手册详细介绍了这个强大的汇编器的使用方法和特点，是学习和精通FASM汇编语言编程的重要参考资料。无论是新手还是经验丰富的程序员，都能从中受益，提升x86汇编编程的技能。

16 CHAPTER 1. INTRODUCTION

1.2.6 Size settings

When instruction uses some memory addressing, by default the smallest form of instruc-

tion is generated by using the short displacement if only address value ﬁts in the range.

This can be overridden using the word or dword operator before the address inside the

square brackets (or after the ptr operator), which forces the long displacement of ap-

propriate size to be made. In case when address is not relative to any registers, those

operators allow also to choose the appropriate mode of absolute addressing.

Instructions adc, add, and, cmp, or, sbb, sub and xor with ﬁrst operand being 16–bit

or 32–bit are by default generated in shortened 8–bit form when the second operand is

immediate value ﬁtting in the range for signed 8-bit values. It also can be overridden

by putting the word or dword operator before the immediate value. The similar rules

applies to the imul instruction with the last operand being immediate value.

Immediate value as an operand for push instruction without a size operator is by

default treated as a word value if assembler is in 16–bit mode and as a double word value

if assembler is in 32–bit mode, shorter 8–bit form of this instruction is used if possible,

word or dword size operator forces the push instruction to be generated in longer form

for speciﬁed size. pushw and pushd mnemonics force assembler to generate 16-bit or

32–bit code without forcing it to use the longer form of instruction.

18 CHAPTER 2. INSTRUCTION SET

destination operand are the same. Below are the examples for each of the allowed

combinations:

mov bx,ax ; general register to general register

mov [char],al ; general register to memory

mov bl,[char] ; memory to general register

mov dl,32 ; immediate value to general register

mov [char],32 ; immediate value to memory

mov ax,ds ; segment register to general register

mov [bx],ds ; segment register to memory

mov ds,ax ; general register to segment register

mov ds,[bx] ; memory to segment register

mov eax,cr0 ; control register to general register

mov cr3,ebx ; general register to control register

xchg swaps the contents of two operands. It can swap two byte operands, two

word operands or two double word operands. Order of operands is not important. The

operands may be two general registers, or general register with memory. For example:

xchg ax,bx ; swap two general registers

xchg al,[char] ; swap register with memory

push decrements the stack frame pointer (esp register), then transfers the operand to

the top of stack indicated by esp. The operand can be memory, general register, segment

value and no size is speciﬁed, it is by default treated as a word value if assembler is

in 16–bit mode and as a double word value if assembler is in 32–bit mode. pushw and

pushd mnemonics are variants of this instruction that store the values of word or double

word size respectively. If more operands follow in the same line (separated only with

spaces, not commas), compiler will assemble chain of the push instructions with these

operands. The examples are with single operands:

push ax ; store general register

push es ; store segment register

pushw [bx] ; store memory

push 1000h ; store immediate value

pusha saves the contents of the eight general register on the stack. This instruction

has no operands. There are two version of this instruction, one 16–bit and one 32–bit,

assembler automatically generates the right version for current mode, but it can be

overridden by using pushaw or pushad mnemonic to always get the 16–bit or 32–bit

version. The 16–bit version of this instruction pushes general registers on the stack in

the following order: ax, cx, dx, bx, the initial value of sp before ax was pushed, bp, si

and di. The 32–bit version pushes equivalent 32–bit general registers in the same order.

2.1. THE X86 ARCHITECTURE INSTRUCTIONS 19

pop transfers the word or double word at the current top of stack to the destination

operand, and then increments esp to point to the new top of stack. The operand can be

memory, general register or segment register. popw and popd mnemonics are variants of

this instruction for restoring the values of word or double word size respectively. If more

operands separated with spaces follow in the same line, compiler will assemble chain of

the pop instructions with these operands.

pop bx ; restore general register

pop ds ; restore segment register

popw [si] ; restore memory

popa restores the registers saved on the stack by pusha instruction, except for the

saved value of sp (or esp), which is ignored. This instruction has no operands. To force

assembling 16–bit or 32–bit version of this instruction use popaw or popad mnemonic.

2.1.2 Type conversion instructions

The type conversion instructions convert bytes into words, words into double words, and

double words into quad words. These conversions can be done using the sign extension

or zero extension. The sign extension ﬁlls the extra bits of the larger item with the

value of the sign bit of the smaller item, the zero extension simply ﬁlls them with zeros.

cwd and cdq double the size of value ax or eax register respectively and store the

extra bits into the dx or edx register. The conversion is done using the sign extension.

These instructions have no operands.

cbw extends the sign of the byte in al throughout ax, and cwde extends the sign of

the word in ax throughout eax. These instructions also have no operands.

movsx converts a byte to word or double word and a word to double word using

the sign extension. movzx does the same, but it uses the zero extension. The source

operand can be general register or memory, while the destination operand must be a

general register. For example:

movsx ax,al ; byte register to word register

movsx edx,dl ; byte register to double word register

movsx eax,ax ; word register to double word register

movsx ax,byte [bx] ; byte memory to word register

movsx edx,byte [bx] ; byte memory to double word register

movsx eax,word [bx] ; word memory to double word register

2.1.3 Binary arithmetic instructions

add replaces the destination operand with the sum of the source and destination operands

and sets CF if overﬂow has occurred. The operands may be bytes, words or double words.

The destination operand can be general register or memory, the source operand can be

20 CHAPTER 2. INSTRUCTION SET

general register or immediate value, it can also be memory if the destination operand is

add ax,bx ; add register to register

add ax,[si] ; add memory to register

add [di],al ; add register to memory

add al,48 ; add immediate value to register

add [char],48 ; add immediate value to memory

adc sums the operands, adds one if CF is set, and replaces the destination operand

with the result. Rules for the operands are the same as for the add instruction. An add

followed by multiple adc instructions can be used to add numbers longer than 32 bits.

inc adds one to the operand, it does not aﬀect CF. The operand can be a general

inc ax ; increment register by one

inc byte [bx] ; increment memory by one

sub subtracts the source operand from the destination operand and replaces the

destination operand with the result. If a borrow is required, the CF is set. Rules for

the operands are the same as for the add instruction.

sbb subtracts the source operand from the destination operand, subtracts one if CF

is set, and stores the result to the destination operand. Rules for the operands are the

same as for the add instruction. A sub followed by multiple sbb instructions may be

used to subtract numbers longer than 32 bits.

dec subtracts one from the operand, it does not aﬀect CF. Rules for the operand are

the same as for the inc instruction.

cmp subtracts the source operand from the destination operand. It updates the ﬂags

as the sub instruction, but does not alter the source and destination operands. Rules

for the operands are the same as for the sub instruction.

neg subtracts a signed integer operand from zero. The eﬀect of this instructon is to

reverse the sign of the operand from positive to negative or from negative to positive.

Rules for the operand are the same as for the inc instruction.

xadd exchanges the destination operand with the source operand, then loads the

sum of the two values into the destination operand. The destination operand may be a

general register or memory, the source operand must be a general register.

All the above binary arithmetic instructions update SF, ZF, PF and OF ﬂags. SF

is always set to the same value as the result’s sign bit, ZF is set when all the bits of

result are zero, PF is set when low order eight bits of result contain an even number of

set bits, OF is set if result is too large for a positive number or too small for a negative

number (excluding sign bit) to ﬁt in destination operand.

mul performs an unsigned multiplication of the operand and the accumulator. If the

operand is a byte, the processor multiplies it by the contents of al and returns the 16–bit

result to ah and al. If the operand is a word, the processor multiplies it by the contents

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