Virtex-7与Kintex-7 FPGA的高效多 IP乘法器设计

需积分: 0 65 浏览量更新于2024-08-05 收藏 283KB PDF 举报

"Mult_IP乘法器1是Xilinx公司提供的LogiCORE IP系列中的一个高性能、可配置的数字乘法器。该产品专为Xilinx的多种FPGA平台设计，包括Virtex-7和Kintex-7系列，以及Virtex-6、Virtex-5、Virtex-4、Spartan-6、Spartan-3/XA、Spartan-3E/XA、Spartan-3A/3AN/3ADSP/XA等不同代际的FPGA器件。这款IP乘法器旨在满足各种应用需求，提供了丰富的功能和优化选项。其主要特点如下： 1. 兼容性：作为一款即插即用模块，用户可以方便地将其集成到上述各系列FPGA中，无需额外的定制工作，简化了设计流程。 2. 数据类型支持：支持固定点的并行乘法运算，适用于二进制补码有符号或无符号数据，灵活性高，适应不同的数据处理场景。 3. 输入/输出宽度：多通道设计，允许输入信号宽度从1位到64位不等，输出信号宽度可选范围从1位到128位，且能选择全产品的任意部分作为输出，以适应不同精度的需求。 4. 可配置性：用户可以根据具体的应用需求，选择合适的乘法器变种，灵活调整其内部结构，实现不同延时性能。这在对速度和资源占用有特殊要求的项目中尤其有用。 5. 资源估算工具：通过Xilinx的CORE Generator工具，设计师可以进行精确的资源估算，了解在目标FPGA上使用该乘法器可能消耗的LUTs、FFs（触发器）和其他逻辑资源，以便进行有效的设计空间探索和优化。 6. 版权与商标：所有内容受版权保护，Xilinx、ISE、MATLAB等均为各自公司的注册商标，确保知识产权的合规性。 Mult_IP乘法器1是一个强大的IP核心，为FPGA设计者提供了一种高效且灵活的解决方案，能够适应各种规模和性能要求的乘法运算任务，显著提高了设计效率和FPGA的使用效率。"

DS255 March 1, 2011 www.xilinx.com 3

Product Specification

LogiCORE IP Multiplier v11.2

CORE Generator Graphical User Interface Parameters

The Multiplier core GUI has several pages with fields to set parameter values for the particular instantiation

required. This section provides a description of each GUI field.

• Component Name: The name of the core component to be instantiated. The name must begin with a letter and

be composed of the following characters: a to z, 0 to 9, and “_”.

• Multiplier Type: Select between parallel and constant-coefficient multiplier options.

• Input Options: Select the required operand widths and whether the operands represent two’s complement

signed or unsigned data.

• Parallel Multiplier Options: These options are visible only when the multiplier type chosen is Parallel

Multiplier.

• Multiplier Construction: Allows the choice of LUTs or dedicated multiplier primitives to be selected for

the core implementation.

• Optimization Options:

- XtremeDSP slice and MULT18X18 multipliers: Speed or area optimization can be selected for

multiplier sizes up to 47x47. Speed optimization makes full use of multiplier primitives to provide the

highest performance implementation. Area optimization uses a mixture of slice logic and dedicated

multiplier primitives to reduce MULT18X18/XtremeDSP slice utilization, while still providing

reasonable performance. For sizes above 47x47, only optimization for speed is allowed.

- LUT-based multipliers: For FPGA devices with LUT6s, area and speed optimization is offered. Area

optimization allows reduced latency and LUT utilization, at the expense of achievable clock frequency.

The area optimization is most effective when both input operands are unsigned. Speed optimization

implements the same architecture for both LUT4 and LUT6 based FPGA devices.

• Constant-Coefficient Multiplier Options: These options are visible only when the multiplier type chosen is

Constant-Coefficient Multiplier.

• Coefficient: Enter the integer value of the coefficient within the limits of the range shown. Positive and

negative coefficients are supported. The input type (signed or unsigned) for the constant (B) port is

automatically configured by the GUI based on the integer constant entered. The user may select whether

the A port is signed or unsigned.

• Memory Options: Select if the multiplier should be implemented with distributed memory, block

memory, or using embedded multiplier blocks.

• Output Product Range: The GUI automatically configures the output product width to represent the full

product, based on the widths of the input operands.

• Use Custom Output Width: The number of product bits can be customized if only a portion of the full

product is required for an application by setting the MSB and LSB range.

• Use Symmetric Rounding: For XtremeDSP slice-based parallel multipliers, the product can be

symmetrically rounded towards infinity if required. This is the same behavior as the MATLAB® software

round function. The multiplier must fit on exactly one XtremeDSP slice (maximum signed operand widths

of 25x18 for Kintex-7, Virtex-7, Virtex-6 and Virtex-5, and 18x18 for Virtex-4 devices), and the LSB of the

product must lie within the full-range product width.

• Pipelining and Control Signals

• Pipeline Stages: Select the level of pipelining for the multiplier instance. The label on the right provides

feedback on the optimum number of pipeline stages for maximum performance. The core assumes that all

inputs are registered.

- Pipeline Stages = 0 implies that the core is combinatorial.

- Pipeline Stages = 1 implies that only the core output is registered.

剩余12页未读，继续阅读

大禹倒杯茶

粉丝: 23
资源: 331

Virtex-7与Kintex-7 FPGA的高效多 IP乘法器设计

project_UHF_ddc.rar_ISE_MULT_GEN_ise工程_uhftxt_下变频 VHDL

8bit整数乘法器（verilog实现）

VHDL IP核乘法器及仿真

CP_3_1_alt_calculate_mult.rar

verilog实现32位无符号乘法器和带符号乘法器

DSP_Mult.rar

float32_mult.v

Mixer_dy_ddc_FPGAverilog_混频滤波_数字滤波器_dy666.38com_

最新资源