PCI Local Bus Specification R2.3：高速接口标准与更新历史

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PCI Local Bus Specification R2.3 是一个高性能的32位或64位总线标准，它专注于在高度集成的外设控制器组件、外围插槽卡以及处理器和内存系统之间提供高速的数据传输和通信接口。该规范的主要特点是采用了多路复用地址和数据线，以支持高效的数据传输。 R2.3 版本是在1992年6月发布的原始版本基础上发展而来，经过多次修订以增强其功能性和兼容性。以下是关键的修订历史： 1. **1.0版 (6/22/92)**：这是初始发布，奠定了基础规范。 2. **2.0版 (4/30/93)**：加入了连接器和扩展板规格，提升了系统的扩展能力。 3. **2.1版 (6/1/95)**：对原有规范进行了澄清，并新增了对66MHz工作的支持，提高了性能上限。 4. **2.2版 (12/18/98)**：引入了错误修正（ECNs，Engineering Change Notifications）并改善了文档的可读性，增强了规范的准确性和易用性。 5. **2.3版 (10/31/01)**：最后一次重大修订，包含了更多的ECNs、错误修正（包括删除仅适用于5V电压环境的插槽卡），旨在解决之前发现的问题并提升标准的适用范围。值得注意的是，PCI Special Interest Group (PCI SIG) 发布此规范时，声明不对其使用承担责任，也不承诺更新其中的信息，除非有新的修订。对于最新的规范版本、关于PCI规范的疑问或者加入PCI SIG，用户应联系PCI SIG办公室获取最准确的信息，地址和联系方式如下： - 地址：5440 SW Westgate Drive, Suite 217, Portland, Oregon 97221 - 联系电话：美国境内800-433-5177，国外503-291-2569 - 传真：503-297-1090 - 电子邮件：[电子邮件地址] PCI Local Bus Specification R2.3 是一个重要的工业标准，对于设计和实现高性能计算机系统中的外设接口至关重要。通过了解它的演变和特点，工程师可以确保他们的硬件设备与现代系统兼容并实现最佳性能。

Revision 2.3

1.3. PCI Local Bus Applications

The PCI Local Bus has been defined with the primary goal of establishing an industry

standard, high performance local bus architecture that offers low cost and allows

differentiation. While the primary focus is on enabling new price-performance points in

today's systems, it is important that a new standard also accommodates future system

requirements and be applicable across multiple platforms and architectures. Figure 1-1

shows the multiple dimensions of the PCI Local Bus.

3.3V

Servers

h End

Deskto

Low, Mid-

Ran

Deskto

X86

Architecture

Processor

Families

ha AXP

Processor

Families

Future

CPUs

64-bit Upgrade

Path

Auto

Confi

uration

Mobile

Figure 1-1: PCI Local Bus Applications

While the initial focus of local bus applications has been on low to high end desktop

systems, the PCI Local Bus also comprehends the requirements from mobile applications

up through servers. The PCI Local Bus specifies both the 3.3 volt and 5 volt signaling

requirements and this revision no longer supports 5 volt only keyed add-in cards, which

represents a significant step in the migration path to the 3.3 volt signaling environment.

The PCI component and add-in card interface is processor independent, enabling an

efficient transition to future processor generations and use with multiple processor

architectures. Processor independence allows the PCI Local Bus to be optimized for I/O

functions, enables concurrent operation of the local bus with the processor/memory

subsystem, and accommodates multiple high performance peripherals in addition to

graphics (motion video, LAN, SCSI, FDDI, hard disk drives, etc.). Movement to

enhanced video and multimedia displays (i.e., HDTV and 3D graphics) and other high

bandwidth I/O will continue to increase local bus bandwidth requirements. A

transparent 64-bit extension of the 32-bit data and address buses is defined, doubling the

bus bandwidth and offering forward and backward compatibility of 32-bit and 64-bit PCI

Local Bus peripherals. A forward and backward compatible PCI-X specification (see the

PCI-X Addendum to the PCI Local Bus Specification

) is also defined, increasing the

bandwidth capabilities of the 33 MHz definition by a factor of four.

The PCI Local Bus standard offers additional benefits to the users of PCI based systems.

Configuration registers are specified for PCI components and add-in cards. A system

with embedded auto configuration software offers true ease-of-use for the system user by

automatically configuring PCI add-in cards at power on.

Revision 2.3

1.5. PCI Local Bus Features and Benefits

The PCI Local Bus was specified to establish a high performance local bus standard for

several generations of products. The PCI specification provides a selection of features

that can achieve multiple price-performance points and can enable functions that allow

differentiation at the system and component level. Features are categorized by benefit as

follows:

High Performance

•

Transparent upgrade from 32-bit data path at 33 MHz

(132 MB/s peak) to 64-bit data path at 33 MHz

(264 MB/s peak), from 32-bit data path at 66 MHz

(264 MB/s peak) to 64-bit data path at 66 MHz

(532 MB/s peak), and from 32-bit data path at 133 MHz

(532 MB/s peak) to 64-bit data path at 133 MHz (1064

MB/s peak).

•

Variable length linear and cacheline wrap mode bursting

for both read and writes improves write dependent

graphics performance.

•

Low latency random accesses (60-ns write access latency

for 33 MHz PCI to 30-ns for 133 MHz PCI-X to slave

registers from master parked on bus).

•

Capable of full concurrency with processor/memory

subsystem.

•

Synchronous bus with operation up to 33 MHz, 66 MHz,

or 133 MHz.

•

Hidden (overlapped) central arbitration.

Low Cost

•

Optimized for direct silicon (component) interconnection;

i.e., no glue logic. Electrical/driver (i.e., total load) and

frequency specifications are met with standard ASIC

technologies and other typical processes.

•

Multiplexed architecture reduces pin count (47 signals for

target; 49 for master) and package size of PCI components

or provides for additional functions to be built into a

particular package size.

Ease of Use

•

Enables full auto configuration support of PCI Local Bus

add-in cards and components. PCI devices contain

registers with the device information required for

configuration.

Longevity

•

Processor independent. Supports multiple families of

processors as well as future generations of processors (by

bridges or by direct integration).

•

Support for 64-bit addressing.

•

Both 5-volt and 3.3-volt signaling environments are

specified. Voltage migration path enables smooth industry

transition from 5 volts to 3.3 volts.

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