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13
ADS7028
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ZHCSJX5 –JUNE 2019
版权 © 2019, Texas Instruments Incorporated
When the ADS7028 detects a CRC error on the SPI interface, the erroneous data are ignored and the
CRCERR_IN bit is set. Additional notifications can be enabled as described in 表 2. Further register writes are
disabled until the CRCERR_IN bit is cleared by writing 1b to this bit. When using autonomous conversion mode,
further conversions can be disabled on a CRC error on the SPI interface by setting CONV_ON_ERR = 1b.
8.3.7 General-Purpose I/Os
The eight channels of the ADS7028 can be independently configured as analog inputs, digital inputs, or digital
outputs. 表 3 shows how the PIN_CFG and GPIO_CFG registers can be used to configure the device channels.
表表 3. Configuring Channels as Analog Inputs or GPIOs
PIN_CFG[7:0] GPIO_CFG[7:0] GPO_DRIVE_CFG[7:0] CHANNEL CONFIGURATION
0 x x Analog input (default)
1 0 x Digital input
1 1 0 Digital output; open-drain driver
1 1 1 Digital output; push-pull driver
Digital outputs can be configured to logic 1 or 0 by writing to the GPO_OUTPUT_VALUE register. Reading the
GPI_VALUE register returns the logic level for all channels configured as digital inputs or digital outputs. The
GPI_VALUE register can be read to detect a failure in external components, such as a floating pullup resistor or
a low-impedance pulldown resistor, that prevents digital outputs being set to the desired logic level.
8.3.8 Oscillator and Timing Control
The device uses an internal oscillator for conversion. When using the averaging module, the host initiates the
first conversion and subsequent conversions are generated internally by the device. Also, in autonomous mode
of operation, the start of the conversion signal is generated by the device. 表 4 describes how the sampling rate
can be controlled by the OSC_SEL and CLK_DIV[3:0] register fields when the device generates the start of the
conversion.
表表 4. Configuring Sampling Rate for Internal Conversion Start Control
CLK_DIV[3:0]
OSC_SEL = 0 OSC_SEL = 1
SAMPLING FREQUENCY, f
CYCLE
(kSPS)
CYCLE TIME,
t
CYCLE
(µs)
SAMPLING FREQUENCY,
f
CYCLE
(kSPS)
CYCLE TIME, t
CYCLE
(µs)
0000b 1000 1 31.25 32
0001b 666.7 1.5 20.83 48
0010b 500 2 15.63 64
0011b 333.3 3 10.42 96
0100b 250 4 7.81 128
0101b 166.7 6 5.21 192
0110b 125 8 3.91 256
0111b 83 12 2.60 384
1000b 62.5 16 1.95 512
1001b 41.7 24 1.3 768
1010b 31.3 32 0.98 1024
1011b 20.8 48 0.65 1536
1100b 15.6 64 0.49 2048
1101b 10.4 96 0.33 3072
The conversion time of the device, given by t
CONV
in the Switching Characteristics table, is independent of the
OSC_SEL and CLK_DIV[3:0] configuration.
8.3.9 Output Data Format
图 6 shows various SPI frames for reading data. The data output is MSB aligned. If averaging is enabled the
output data from the ADC are 16 bits long, otherwise the output data are 12 bits long. Optionally, a 4-bit channel
ID or status flags can be appended at the end of the output data by configuring the APPEND_STATUS[1:0] field.