55nm CMOS异步SAR ADC：9.1ENOB 200MS/s图像传感器解决方案

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本文档介绍了一篇关于"具有55纳米CMOS工艺的混合单端/差分DAC的9.1ENOB (有效位数) 200MS/s (每秒采样率) 异步 Successive Approximation Register (SAR) 数模转换器(A/D转换器)"的研究论文。该论文针对的是图像传感器信号处理应用，设计了一个高度集成的高性能A/D转换器。主要特点包括： 1. 技术实现：采用先进的55纳米CMOS工艺，这允许在紧凑的芯片面积上实现高效能和低功耗的设计。 2. 工作模式：设计具有灵活性，能够以单端模式和差分模式工作，适应不同类型的图像传感器信号输入，提高了系统的兼容性。 3. 线性度增强：为了确保转换的精度，采用了不对称开关方法来改善线性性能，这对于图像信号处理中的关键特性至关重要。 4. 参考电压稳定性：为了保持高精度，文中提到集成了一款1.2V的快速响应降压稳压器（LDO），即使在2.5V供电条件下也能提供稳定的参考电压。 5. 异步操作：为了避免高速时钟电路和接口电路的设计复杂性，论文选择异步时钟逻辑，简化了系统架构，并减少了对外部时钟源的依赖。 6. 动态比较周期调整：通过动态调整比较周期，能够在保持 DAC (数字模拟转换器) 清晰度的同时，优化A/D转换的吞吐量，提高整体效率。 7. 性能指标：在差分模式下，该SAR ADC达到了峰值信噪比(SNDR)高达56分贝，显示出卓越的信号质量，这对于图像传感器来说是非常关键的性能指标。总结来说，这篇研究论文提供了对一个高性能、低功耗且易于集成的图像传感器专用A/D转换器的深入探讨，它不仅满足了图像处理应用的需求，还展示了CMOS工艺在高级混合信号设计中的优势。这样的技术对于推动图像传感器领域的发展具有重要意义。

7132 IEEE SENSORS JOURNAL, VOL. 18, NO. 17, SEPTEMBER 1, 2018

Fig. 3. Proposed switching procedure for a 4-bit SAR ADC in differential operation mode.

common-mode noise, failure to suppress the even harmon-

ics and the reduced signal swing. Hence, for low-resolution

and power-hungry cases, the single-ended architecture is pre-

ferred, while the differential architecture is suitable for high-

resolution cases.

The proposed switching procedure for the 4-bit SAR ADC

in differential operation mode is illustrated in Fig. 3. Each

capacitive DAC is split into two identical halves. To cut

the number of capacitors in the DACs, the top-plate sam-

pling method is adopted. The speciﬁc switching procedure is

described as follows:

(1) During the sampling phase (CLK = “1”), the top

plates of all the capacitors sample the inputs, Vip and Vin.

Meanwhile, the bottom plates of the capacitors in the C

and C

parts are initially loaded with the sequence of

[Vref , Vref ,...,Vref ], and the bottom plates of the capacitors

in the complementary parts, C

and C

, are loaded with the

sequence of [0, 0,...,0].

(2) When the CLK becomes low, the conversion phase

arrives. The comparator does the comparison under the con-

trol of the CLK_COMP signal. On account of the top-plate

sampling, the MSB bit D3 is obtained directly without any

switching action when the ﬁrst rising edge of CLK_COMP

comes. If Vp > Vn (D3 = “1”), the bottom plate of C

PA1

is switched from Vrefto GND, while the bottom plate of

NA1

is switched from GND to Vref. Consequently, (Vp-Vn)

is decreased by 1/2 Vref. The case of Vp < Vn (D3 = “0”) is

performed similarly.

(3) The second comparison cycle is triggered to start by

the next rising edge of the CLK_COMP and the (MSB-1)

bit D2 is determined. At this time, if Vp > Vn (D2 = “1”),

the voltage on the bottom plate of C

PA2

is reduced by Vref

(from Vrefto “0”), the voltage on the bottom-plate of C

NA2

brought up to Vref (from “0” toVref). This operation lowers

(Vp-Vn)by1/4Vref. Similar operation is performed with regard

to the case of Vp < Vn (D2 = “0”).

(4) After D1 is determined, a ±1/8Vref change in (Vp-Vn)is

required to bring about for D0 decision. Therefore, the voltage

on the bottom plate of either C

PB3

or C

NA3

raised by Vref will

be eligible.

It is known that the linearity of the SAR ADC depends on

both the speciﬁc switching procedure and the mismatch among

the capacitors in the DACs [7]. Assume that the error term δ

corresponding to the unit capacitor Cu satisﬁes

(

)

= σ

(1)

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