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A Real-Time FPGA-Based Accelerator for ECG Analysis 25:5
multiple clients in huge quantities. The FPGA-based accelerator is connected to the
server and responsible for analyzing signals and giving diagnosis results before send-
ing the results to the server. Then, the s erver can return the diagnosis results to clients,
or hospitals if any emergency is detected. Also, we are hoping that the data-analyzing
results can be stored in a database, which is helpful for medical research.
The problem that we intend to address is how to build a hardware accelerator that
meets the following requirements:
(1) The design should be able to handle massive signals sent from the cloud or server;
(2) The latency issue growing with the increasing quantity of data s hould be solved;
(3) The implementation should have good scalability to catch up with the growing
bandwidth of data transmission, which means that the size of the signals should
not affect its average performance or hardware architecture.
(4) The implementation needs to keep a sustainable power efficiency given scalable
amounts of data requests.
(5) Adaptability in terms of analysis-rule updating is also expected in the
implementation.
To meet these requirements, we propose the following solutions:
—To process massive signals, we implemented multiple pipelines on FPGAs, each of
which processes a flow of signals in a pipelining style. Since there is only one interface
between a server and an FPGA, a scheduling mechanism for data should be figured
out to ensure that pipelines are used at full capacity.
—We improved the data-analyzing algorithms, including the ECG feature extraction
algorithm and data-mining algorithm. These algorithms should be transformed to
be more suitable for parallel implementation. In addition, data formats of these
algorithms should be regular, which is important for hardware design.
—To have satisfactory scalability, streaming architecture is adopted in the design.
Moreover, data transmission bandwidth between server and FPGA should be high
enough to avoid becoming a bottleneck in the system. Therefore, PCI-E is employed
as a communication strategy.
—Since all the resources in FPGA can be configured as on or off, an FPGA-based accel-
erator design is adopted to expose a better power efficiency than other accelerators
such as a GPU, given a dynamic level of incoming workloads.
Based on these solutions, we apply wavelet transform to extract ECG features and
propose the Bit-Q-Apriori algorithm to mine association rules, which are further used
to diagnose ECGs. The FPGA-based implementation is a streaming architecture, with
multiple pipelines working simultaneously. To alleviate data I/O bottleneck, we apply
multiple storage strategies to provide high memory bandwidth within FPGA. We also
explore FPGAs’ inherent features to complete a huge amount of parallel calculation.
The flow of ECG signal processing is composed of three procedures: ECG feature
extraction, association-rule mining, and feature matching, whose corresponding hard-
ware implementation will be explained in detail in Sections 5.2, 5.3, and 5.4 after we
highlight our novel mining algorithm in Section 4.
4. ASSOCIATION-RULE MINING ALGORITHM
4.1. Basic Concepts
Association-rule mining is a popular method for discovering existing relations among
large databases. The original motivation for association-rule mining arose from su-
permarket transaction analysis. For example, a rule discovered for the supermarket
{butter, bread} ⇒ {milk}, means that a customer who buys butter and bread also tends
ACM Transactions on Embedded Computing Systems, Vol. 15, No. 2, Article 25, Publication date: February 2016.