CACTI-3DD：3D DRAM 主存建模与性能分析工具

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"CACTI3DD是一款专用于3D DRAM存储器设计的高级建模工具，由来自University of Notre Dame、Hewlett-Packard Labs和Seoul National University的研究人员开发。它提供了全面的电源、面积和时序模型，支持从粗粒度的级联层次3D堆叠到细粒度的银行级别3D堆叠的各种3D DRAM设计方案的分析。通过CACTI-3DD，可以深入研究3D堆叠DRAM设计中的架构级权衡，以满足性能、功率和成本的不断增长需求。" 3D DRAM技术是应对未来内存架构挑战的关键解决方案之一，尤其是在满足性能、功耗和成本方面的需求上。CACTI-3DD是第一个针对3D叠层离片DRAM主存的架构级集成功率、面积和时序建模框架。该工具引入了硅通孔（TSV）模型，对现有的CACTI版本中2D离片DRAM主存模型进行了改进，并包含了3D集成模型，允许用户分析一系列3D DRAM设计。 CACTI-3DD的主要特点包括： 1. **TSV模型**：TSV（Through Silicon Via）是3D DRAM堆叠中的关键组成部分，CACTI-3DD提供了TSV的建模，以准确评估其对整体性能、功耗和面积的影响。 2. **2D DRAM模型升级**：与现有CACTI版本相比，CACTI-3DD对2D离片DRAM模型进行了优化，提高了模型的精度和适用性。 3. **3D集成模型**：这使得研究人员和工程师能够探索不同级别的3D堆叠，从较粗粒度的级联层次堆叠到更精细的银行级别堆叠，从而研究不同设计选项的性能差异。 4. **架构级权衡分析**：CACTI-3DD的核心功能之一是提供对3D DRAM设计中电源、面积和时序的深度研究，帮助决策者在设计过程中做出最优选择。此外，CACTI-3DD的实用性在文中通过案例研究得到验证，证明了它在评估3D DRAM设计的性能、功耗和面积之间权衡时的价值。这一工具对于推动3D DRAM技术的发展，优化内存系统架构，以及在学术和工业界进行先进内存设计研究具有重要意义。 CACTI-3DD是3D DRAM领域的重要工具，为研究人员和工程师提供了一个全面的平台，以应对内存系统设计中的复杂挑战，促进3D DRAM技术的创新和应用。

CACTI-3DD: Architecture-level Modeling

for 3D Die-stacked DRAM Main Memory

Ke Chen

‡†

, Sheng Li

†

, Naveen Muralimanohar

†

, Jung Ho Ahn

, Jay B. Brockman

‡

, Norman P. Jouppi

†

‡

University of Notre Dame,

†

Hewlett-Packard Labs,

Seoul National University

‡

{kchen2, jbb }@nd.edu,

†

{kec, sheng.li4, naveen.muralimanohar, norm.jouppi}@hp.com,

gajh@snu.ac.kr

Abstract—Emerging 3D die-stacked DRAM technology is one of the

most promising solutions for future memory architectures to satisfy the

ever-increasing demands on performance, power, and cost. This paper

introduces CACTI-3DD, the ﬁrst architecture-level integrated power,

area, and timing modeling framework for 3D die-stacked off-chip DRAM

main memory. CACTI-3DD includes TSV models, improves models for

2D off-chip DRAM main memory over current versions of CACTI, and

includes 3D integration models that enable the analysis of a full spectrum

of 3D DRAM designs from coarse-grained rank-level 3D stacking to bank-

level 3D stacking. CACTI-3DD enables an in-depth study of architecture-

level tradeoffs of power, area, and timing for 3D die-stacked DRAM

designs. We demonstrate the utility of CACTI-3DD in analyzing design

trade-offs of emerging 3D die-stacked DRAM main memories. We ﬁnd

that a coarse-grained 3D DRAM design that stacks canonical DRAM dies

can only achieve marginal beneﬁts in power, area, and timing compared

to the original 2D design. To fully leverage the huge internal bandwidth of

TSVs, DRAM dies must be re-architected, and system implications must

be considered when building 3D DRAMs with redesigned 2D planar

DRAM dies. Our results show that the 3D DRAM with re-architected

DRAM dies achieves signiﬁcant improvements in power and timing

compared to the coarse-grained 3D die-stacked DRAM.

Keywords: 3D architecture, DRAM, TSV, Main memory, Modeling

I. INTRODUCTION

Modern computer systems demand ever-increasing performance,

power-efﬁciency, and capacity from Dynamic Random Access Mem-

ories (DRAMs) to meet system performance requirements. As

Moore’s Law drives CMOS technology into the deep nanoscale

regime, DRAM scaling faces serious challenges in speed, bandwidth,

capacity, and cost. For example, historically CPU performance has

improved at an annual rate of 55% while the memory access time

has only improved by 10%, resulting in the well-known memory wall

problem [6]. Moreover, for decades DRAM capacity had increased

4× every 3 years, but is now scaling much more slowly [6], resulting

in a memory capacity wall problem. Power and cost of DRAMs are

also facing similar challenges [6].

The DRAM industry has continued to innovate both technologies

and architectures in order to scale the performance, power, capacity

and cost of DRAMs as shown in Table I. New materials and

fabrication processes have been steadily introduced. Hierarchical

978-3-9810801-8-6/DATE12/

2012 EDAA

Ke Chen and Jay Brockman are partially supported by the C2S2 Focus Center,

one of six research centers funded under the Focus Center Research Program

(FCRP), a Semiconductor Research Corporation entity.

This material is based upon work supported by the Department of Energy

under Award Number DE - SC0005026. The disclaimer can be found at http:

//www.hpl.hp.com/DoE-Disclaimer.html

Jung Ho Ahn was supported by the Smart IT Convergence System Research

Center funded by the Ministry of Education, Science and Technology as

Global Frontier Project.

Innovations Tech Gens (nm)

Hierarchical wordline [7] 200

Interface from DDR to DDR2, DDR3 [5], [8] 100 & 65

Varying number of cells per bitline [18] 90

Cell size from 8F

, to 6F

and 4F

[14] 65 & 36

3D stacking [17] 50

Copper metallization [14] 44

High-k dielectric gate oxide [14] 31

TABLE I

DRAM TECHNO LOGY/ARCHITECTURE INNOVATIONS AND THE

TECHNOLOGY GENERATIONS WHEN THE INNOVATION WERE(WILL BE)

WIDELY USED. THE LAST TWO ROWS ARE FUTURE MILESTONES

ACCORDING TO ITRS [14]. THE SELECT ED REFERENCES ARE

REPRESENTATIVE DESIGNS BUT NOT NECESSARILY THE FIRST DESIGN.

wordlines and datalines were incorporated to maintain a steady trend

of increasing DRAM capacity [7]. Motivated to lower the cost and in-

crease the density of DRAM, the DRAM cell size is decreasing from

to 6F

and then to 4F

[14]. The memory interface itself has seen

numerous advances from SDRAM to DDR through the upcoming

DDR4 standard. The wide adoption of multicore processors renders

memory bandwidth and capacity even more critical. Indicative of this

trend, conservative DRAM manufacturers are adopting more radical

technologies such as 3D die-stacked DRAM [10], [17].

Despite technology advances from the DRAM industry, the ability

to propose and evaluate new DRAM designs and their system

implications is currently limited by the availability and quality of

appropriate system-level tools. CACTI-D [15] built a solid founda-

tion for modeling DRAM technologies, including cells and DRAM

subarrays. However, since its peripheral circuit models including

the control path and data path were inherited from SRAM models,

CACTI-D’s overall DRAM model is more appropriate for embedded

DRAM than off-chip DRAM main memory. Correct modeling of the

peripheral circuits including hierarchical wordlines and datalines are

critical, since peripheral circuits play a critical role in determining

the overall power, area, and timing. For example, modern DRAM

designs usually achieve an area efﬁciency of approximately 50% [14].

Vogelsang [18] partially addressed this problem by developing a

power model with detailed peripheral circuit models for DRAM

main memories. However, this model is only for power and does not

estimate timing and area of a DRAM design, which is insufﬁcient

since power, area, and timing are inseparable for modern DRAMs.

Especially important today is the ability to model emerging 3D

die-stacked DRAM technology [10], [17], which shows tremendous

promise for addressing performance, power, and capacity challenges

in the near future. Tsai et. al [16] extended an earlier CACTI

version to model 3D die-stacked SRAMs. However, 3D DRAM is

substantially different from 3D SRAM in the memory cell physics,

fabrication technology, circuit implementation, memory organization,

and peripheral circuit arrangements. Thus, a 3D SRAM model pro-

vides an inadequate basis for modeling 3D die-stacked DRAM [10],

[17].

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