TW8820：多功能视频门铃控制器数据手册

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TW8820是一款专为多功能视频对讲门铃系统设计的集成电路（IC）数据手册，由Intersil Americas Inc.于2011年10月发布初步版本，日期为2012年2月8日。该产品旨在满足高要求的视频门铃显示屏控制器应用，如视频对讲机、便携式DVD和DVR播放器以及移动媒体播放器。这款集成IC的主要特性包括： 1. 高性能2D组合解码器：支持NTSC、PAL和SECAM三种标准格式，确保在不同地区都能提供清晰的图像质量。 2. 图像增强功能：内置功能如黑白拉伸技术，可以改善显示效果，提高图像的对比度和细节表现力。 3. 宽屏适应性：支持全景比例缩放，使得输出画面能够无缝适应宽屏显示器，提供出色的观看体验。 4. 输入兼容性：具备复合视频输入（CVBS）接口，能够接收来自门铃摄像头的模拟信号。 5. 输出灵活性：集成定时控制器，支持多种数字面板类型，这使得它能与各种现有的或定制的面板系统无缝连接。 6. 高度集成：所有这些功能都集中在单个芯片上，简化了系统设计，减少了外部组件的需求，提高了系统的稳定性和成本效益。在安全方面，产品提醒用户注意静电防护，因为敏感的电子元件易受静电损害，建议遵循正确的集成电路处理程序以避免潜在问题。版权方面，Intersil及其标志是Intersil Corporation或其子公司的商标，其他提及的商标属于各自所有者所有。TW8820是一款专为LCD控制器市场设计的创新产品，体现了Intersil在音频视频处理领域的专业技术。 TW8820是一款高度集成且功能丰富的视频门铃控制器，适用于追求高质量显示效果和简便设计的多种应用场合。通过它的全面特性，制造商能够快速开发出具有竞争力的视频对讲解决方案。

TW8820

OSD Window Start Location: Built-in OSD controller

o Internal generated OSD DE Position delayed from H-SYNC: 0x303[7:0].

o OSD window H_start location from start of internal OSD DE: 0x312[6:4], 0x313[7:0] increment by 1 pixel

at a time.

o OSD window V_start location from start of VACT: 0x312[1:0], 0x314[7:0] increment by 1 line at a time.

Address

The characters can be displayed on the screen in four user

defined window locations of any size from 1 to 256

characters. There is a limit of 256 characters that may be

displayed on screen at one time in all windows combined.

Example

Window #1: Address 0 – 2 (3 characters)

Window #2: Address 3 – 100 (98 characters)

Window #3: Address 101– 154 (54 characters)

Window #4: Address 255 (1 character)

OSD_RAM Configuration

253

254

255

8 7

FONT_ADDRESS (10-bits)

Bit 17: Border/Shadow

Bit 16: Blinking

Bit 15 - 8: FONT Address

FONT_ATTRIBUTE (8-bits)

Bit 7-4 : Character’s background color

Bit 3-0 : Character’s foreground color

TW8820

Figure 3. One complete register Read sequence via the serial bus interface

The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read

control or other information from the internal registers. MC_SCLK is the serial clock and MC_SDA is the data

line. Both lines are pulled high by resistors connected to VDD. ICs communicate on the bus by pulling

MC_SCLK and MC_SDA low through open drain outputs. In normal operation the master generates all clock

pulses, but control of the MC_SDA line alternates back and forth between the master and the slave. For both

read and write, each byte is transferred MSB first, and the data bit is valid whenever MC_SCLK is high.

The device is operated as a bus slave device. The 7-bit device address field is fixed and concatenated with the

read/write control bit to form the first byte transferred during a new transfer. If the read/write control bit is

high the next byte will be read from the slave device. If it is low the next byte will be a write to the slave. When

a bus master (the host microprocessor) drives MC_SDA from high to low, while MC_SCLK is high, this is

defined to be a start condition (See Figure 1.). All slaves on the bus listen to determine when a start condition

has been asserted.

After a start condition, all slave devices listen for their device addresses. The host then sends a byte

consisting of the 7-bit slave device ID and the R/W bit. This is shown in Figure 2. (The next byte is normally the

index to the internal registers and is a write to the device therefore the first R/W bit is normally low.)

After transmitting the device address and the R/W bit, the master must release the MC_SDA line while holding

MC_SCLK low, and wait for an acknowledgement from the slave. If the address matches the device address of

a slave, the slave will respond by driving the MC_SDA line low to acknowledge the condition. The master will

then continue with the next 8-bit transfer. If no device on the bus responds, the master transmits a stop

condition and ends the cycle. Notice that a successful transfer always includes nine clock pulses.

To write to the internal register, the master sends another 8-bit of data, it loads this to the register pointed by

the internal index register. The device will acknowledge the 8-bit data transfer and automatically increment

the index in preparation for the next data. The master can do multiple writes if they are in ascending

sequential order. After each 8-bit transfer the device will acknowledge the receipt of the 8-bits with an

acknowledgement pulse. To end all transfers, the host has to issue a stop condition.

Re-start

Condition

MC_SCLK

Device ID (1-7)

R/W

Index (1-8)

MC_SDA

Ack

Data (1-8)

Stop

Condition

Nack

Start

Condition

Device ID (1-7)

R/W

Ack

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