CS8414 96 kHz 数字音频接收器技术规格

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"CS8414是一款96kHz数字音频接收器，由Cirrus Logic公司制造，适用于AES/EBU、IEC958、S/PDIF和EIAJ CP340/1201等专业和消费级音频格式。该设备具有低抖动的片上时钟恢复功能，提供256xFs输出时钟，并具有丰富的错误报告机制。在发生错误时，可以选择重复最后一个采样。此外，CS8413还配备了可配置的内部缓冲存储器，通过并行端口读取，用于缓存通道数据。" CS8414 96 kHz Digital Audio Receiver是一款高性能的集成电路，设计用于接收和解码高达96kHz的数字音频信号。这款芯片集成了多种功能，使其能够处理多种数字音频接口标准，包括AES/EBU（音频工程学会/电子广播联盟）用于专业音频应用，以及IEC958（国际电工委员会标准）和S/PDIF（同轴数字接口）以及EIAJ CP340/1201标准，适用于消费级音频设备。一个关键特性是其低抖动的片上时钟恢复系统，这确保了音频信号的高精度和稳定性。256xFs输出时钟的提供使得系统能够准确地同步到输入数据流，这对于高质量的数字音频处理至关重要。此外，CS8414还提供了广泛的错误报告功能，能够检测并报告传输过程中的任何异常，增强了系统的可靠性和故障诊断能力。 CS8413与CS8414在功能上相似，但增加了可配置的内部缓冲存储器。这个特性允许设备在接收音频数据时进行缓冲，防止因数据速率不匹配或瞬时干扰导致的数据丢失。通过并行端口，用户可以读取和控制这些缓冲区，为系统设计提供了更大的灵活性。在物理接口方面，CS8413和CS8414支持差分和单端输入，这意味着它们可以适应各种连接方案。同时，它们与CS8411和CS8412保持引脚兼容性，简化了升级和替换的过程，对于已经使用这些型号的系统来说，这是一个非常实用的设计考虑。 CS8414和CS8413是针对高分辨率数字音频应用而设计的高效接收器，它们结合了先进的时钟恢复技术、丰富的错误处理机制和灵活的内存配置，旨在为音频设备制造商提供可靠的解决方案，以实现卓越的音质和稳定性。

CS8413 CS8414

DS240F1 7

GENERAL DESCRIPTION

The CS8413/14 are monolithic CMOS circuits that

receive and decode audio and digital data accord-

ing to the AES/EBU, IEC 958, S/PDIF, and EIAJ

CP340/1201 interface standards. Both chips con-

tain RS422 line receivers and Phase-Locked Loops

(PLL) that recover the clock and synchronization

signals, and de-multiplex the audio and digital data.

The CS8413 contains a configurable internal buffer

memory, read via a parallel port, which can buffer

channel status, user, and optionally auxiliary data.

The CS8414 de-multiplexes the channel status, us-

er, and validity information directly to serial output

pins with dedicated pins for the most important

channel status bits. Both chips also contain exten-

sive error reporting as well as incoming sample fre-

quency indication for auto-set applications.

The CS8413/14 are pin-compatible with the

CS8411/12 digital audio receiver parts. The func-

tionality of the CS8413/14 is the same as the

CS8411/12 with two exceptions: first, the operat-

ing frequency (sample rate) of the CS8413/14 is ex-

tended to include 96 kHz, and second, the

frequency reporting bits are modified to delete the

±400 ppm ranges, and include 88.2 kHz and

96 kHz ranges.

Familiarity with the AES/EBU and IEC 958 speci-

fications are assumed throughout this document.

The App Note, Overview of Digital Audio Inter-

face Data Structures, contains information on digi-

tal audio specifications; however, it is not meant to

be a complete reference. To guarantee compliance,

the proper standards documents should be ob-

tained. The AES/EBU standard, AES3-1985,

should be obtained from the Audio Engineering

Society or ANSI (ANSI document # ANSI S4.40-

1985); the IEC 958 standard from the International

Electrotechnical Commission; and the EIAJ

CP340/1201 standard from the Japanese Electron-

ics Bureau.

Line Receiver

The RS422 line receiver can decode differential as

well as single ended inputs. The receiver consists

of a differential input Schmitt trigger with 50mV of

hysteresis. The hysteresis prevents noisy signals

from corrupting the phase detector. Appendix A

contains more information on how to configure the

line receivers for differential and single ended sig-

nals.

Clocks and Jitter Attenuation

The primary function of these chips is to recover

audio data and low jitter clocks from a digital audio

transmission line. The clocks that can be generated

are MCK (256xF

), SCK (64xF

), and FSYNC (F

or 2xF

). MCK is the output of the voltage con-

trolled oscillator which is a component of the PLL.

The PLL consists of phase and frequency detectors,

a second-order loop filter, and a voltage controlled

oscillator. All components of the PLL are on chip

with the exception of a resistor and capacitor used

in the loop filter. This filter is connected between

the FILT pin and AGND. The typical closed-loop

transfer function, which specifies the PLL’s jitter

attenuation characteristics, is shown in Figure 3.

Most jitter introduced by the transmission line is

high in frequency and will be strongly attenuated.

Multiple frequency detectors are used to minimize

the time it takes the PLL to lock to the incoming

data stream and to prevent false lock conditions.

When the PLL is not locked to the incoming data

stream, the frequency detectors pull the VCO fre-

quency within the lock range of the PLL. When no

digital audio data is present, the VCO frequency is

pulled to its minimum value.

As a master, SCK is always MCK divided by four,

producing a frequency of 64xF

. In the CS8413,

FSYNC can be programmed to be a divided version

of MCK or it can be generated directly from the in-

coming data stream. In the CS8414, FSYNC is al-

ways generated from the incoming data stream.

When FSYNC is generated from the data, its edges

CS8413 CS8414

8 DS240F1

are extracted at times when intersymbol interfer-

ence is at a minimum. This provides a sample fre-

quency clock that is as spectrally pure as the digital

audio source clock for moderate length transmis-

sion lines. For long transmission lines, the CS8413

can be programmed to generate FSYNC from

MCK instead of from the incoming data.

CS8413 DESCRIPTION

The CS8413 is more flexible than the CS8414 but

requires a microcontroller or DSP to load internal

registers. The CS8414 does not have internal regis-

ters so it may be used in a stand-alone mode where

a microprocessor or DSP is not available.

The CS8413 accepts data from a transmission line

coded according to the digital audio interface stan-

dards. The I.C. recovers clocks and data, and sepa-

rates the audio data from control information. The

audio data is output through a configurable serial

port and the control information is stored in internal

dual-port RAM. Extensive error reporting is avail-

able via internal registers with the option of repeat-

ing the last sample when an error occurs. A block

diagram of the CS8413 is shown in Figure 4

Parallel Port

The parallel port accesses two status registers, two

interrupt enable registers, two control registers, and

28 bytes of dual-port buffer memory. The status

registers and interrupt enable registers occupy the

same address space. A bit in control register 1 se-

lects the two registers, either status or interrupt en-

able, that occupy addresses 0 and 1 in the memory

map. The address bus and the RD/WR line should

be valid when CS goes low. If RD/WR is low, the

value on the data bus will be written into the buffer

memory at the specified address. If RD/WR is high,

the value in the buffer memory, at the specified ad-

dress, is placed on the data bus. Detailed timing for

the parallel port can be found in the Switching

Characteristics - Parallel Port table.

The memory space on the CS8413 is allocated as

shown in Figure 5. There are three defined buffer

modes selectable by two bits in control register 1.

Further information on the buffer modes can be

found in the Control Registers section.

-30

-25

-20

-15

-10

-5

Jitter Frequency (Hz)

Jitter Attenuation (dB)

Figure 3. Typical Jitter Attenuation Characteristics

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