MCP25625 CAN控制器：集成SPI和CAN收发器

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"MCP25625是Microchip Technology公司推出的一款集成CAN（Controller Area Network）控制器和物理层收发器的独立芯片，适用于CAN 2.0B协议。这款芯片具有高效能、低功耗的特点，适用于需要高速通信且对电源效率有要求的嵌入式系统中。通过SPI（Serial Peripheral Interface）接口与微控制器进行通讯，支持高达10MHz的SPI时钟速度。" MCP25625的主要特性包括： 1. **独立CAN控制器**：集成了CAN控制器和CAN收发器，能够直接处理CAN协议，无需额外的硬件支持。 2. **高速操作**：最大工作速率可达1Mb/s，满足高速通信需求。 3. **极低待机电流**：在典型情况下，待机电流仅为10µA，有利于延长电池寿命或降低系统功耗。 4. **SPI接口**：支持SPI模式0、0和1、1，可以与使用2.7V至5.5V I/O电平的微控制器直接连接。 5. **封装形式**：提供SSOP-28和6x6 QFN-28L两种封装选择，适应不同设计需求。 6. **温度范围**：扩展级温度范围为-40°C到+125°C，确保在恶劣环境下稳定工作。 CAN控制器特性： 1. **电压范围**：工作电压为2.7V到5.5V，兼容多种电源标准。 2. **遵循CAN 2.0B规范**：符合国际标准ISO 11898-1，支持数据传输和错误检测功能。 3. **三路发送缓冲区**：带有优先级和中止功能，确保数据传输的有序和可控。 4. **两路接收缓冲区**：用于接收CAN总线上的数据。 5. **六滤波器和两掩码**：可选的前两个数据字节过滤，增强数据过滤和接收精度。 6. **SPI命令优化**：通过特定的SPI指令减少SPI通信的开销。 7. **GPIO配置**：缓冲区满和请求发送引脚可配置为通用输入/输出，提高灵活性。 8. **中断输出引脚**：提供一个中断输出，用于指示重要事件。 CAN收发器特性： 1. **VDDA电压范围**：4.5V到5.5V，符合物理层标准。 2. **符合ISO-11898-2和ISO-11898-5**：实现标准物理层要求，保证信号传输质量。 3. **总线保护**：设备未供电时，CAN总线引脚断开，防止未激活节点加载总线。 4. **地故障检测**：能够检测地线故障，提高系统安全性。综上，MCP25625是一款高集成度、高性能的CAN控制器，适用于汽车电子、工业自动化、楼宇自动化等需要可靠CAN通信的领域。其低功耗特性使得它在电池供电的系统中特别有用，而SPI接口则使得与各种微控制器的集成变得简单。

 2014-2019 Microchip Technology Inc. DS20005282C-page 15

MCP25625

3.7 Message Reception

The registers required for message reception

are described in Section 4.2 “Message Receive

Registers”.

3.7.1 RECEIVE MESSAGE BUFFERING

The MCP25625 includes two full receive buffers with

multiple acceptance filters for each. There is also a

separate Message Assembly Buffer (MAB) that acts as

a third receive buffer (see Figure 3-6).

3.7.1.1 Message Assembly Buffer

Of the three receive buffers, the MAB is always

committed to receiving the next message from the bus.

The MAB assembles all messages received. These

messages will be transferred to the RXBx buffers (see

Registers 4-12 to 4-17) only if the acceptance filter

criteria is met.

3.7.1.2 RXB0 and RXB1

The remaining two receive buffers, called RXB0 and

RXB1, can receive a complete message from the

protocol engine via the MAB. The MCU can access one

buffer, while the other buffer is available for message

reception, or for holding a previously received

message.

3.7.1.3 Receive Flags/interrupts

When a message is moved into either of the receive

buffers, the appropriate RXxIF bit in the CANINTF reg-

ister is set. This bit must be cleared by the MCU in

order to allow a new message to be received into the

buffer. This bit provides a positive lockout to ensure

that the MCU has finished with the message before the

CAN controller attempts to load a new message into

the receive buffer.

If the RXxIE bit in the CANINTE register is set, an inter-

rupt will be generated on the INT

pin to indicate that a

valid message has been received. In addition, the

associated R

xnBF pin will drive low if configured as a

receive buffer full pin. See Section 3.7.4 “Rx0BF and

Rx1BF Pins” for details.

3.7.2 RECEIVE PRIORITY

RXB0, the higher priority buffer, has one mask and two

message acceptance filters associated with it. The

received message is applied to the mask and filters for

RXB0 first.

RXB1 is the lower priority buffer, with one mask and

four acceptance filters associated with it.

In addition to the message being applied to the RB0

mask and filters first, the lower number of acceptance

filters makes the match on RXB0 more restrictive and

implies a higher priority for that buffer.

When a message is received, the RXBxCTRL[3:0] bits

will indicate the acceptance filter number that enabled

reception and whether the received message is a

remote transfer request.

3.7.2.1 Rollover

Additionally, the RXB0CTRL register can be configured

such that, if RXB0 contains a valid message and

another valid message is received, an overflow error

will not occur and the new message will be moved into

RXB1, regardless of the acceptance criteria of RXB1.

3.7.2.2 RXM[1:0] Bits

The RXM[1:0] bits in the RXBxCTRL register set

special Receive modes. Normally, these bits are

cleared to ‘00’ to enable reception of all valid messages

as determined by the appropriate acceptance filters. In

this case, the determination of whether or not to receive

standard or extended messages is determined by the

EXIDE bit in the RFXxSIDL register.

If the RXMx bits are set to ‘11’, the buffer will receive all

messages, regardless of the values of the acceptance

filters. Also, if a message has an error before the End-

of-Frame (EOF), that portion of the message

assembled in the MAB before the error frame will be

loaded into the buffer. This mode has some value in

debugging a CAN system and would not be used in an

actual system environment.

Setting the RXMx bits to ‘01’ or ‘10’ is not

recommended.

Note: The entire content of the MAB is moved

into the receive buffer once a message is

accepted. This means that regardless of

the type of identifier (Standard or

Extended) and the number of data bytes

received, the entire receive buffer is

overwritten with the MAB contents.

Therefore, the contents of all registers in

the buffer must be assumed to have been

modified when any message is received.

MCP25625

DS20005282C-page 16  2014-2019 Microchip Technology Inc.

3.7.3 START-OF-FRAME SIGNAL

If enabled, the Start-of-Frame signal is generated on

the SOF bit at the beginning of each CAN message

detected on the RxCAN pin.

The RxCAN pin monitors an Idle bus for a Recessive-

to-Dominant edge. If the Dominant condition remains

until the sample point, the MCP25625 interprets this as

a SOF and a SOF pulse is generated. If the Dominant

condition does not remain until the sample point, the

MCP25625 interprets this as a glitch on the bus and no

SOF signal is generated. Figure 3-5 illustrates SOF

signaling and glitch filtering.

As with One-Shot mode, one use for SOF signaling is

for TTCAN-type systems. In addition, by monitoring

both the RxCAN pin and the SOF bit, an MCU can

detect early physical bus problems by detecting small

glitches before they affect the CAN communication.

3.7.4 Rx0BF AND Rx1BF PINS

In addition to the INT pin, which provides an interrupt

signal to the MCU for many different conditions, the

Receive Buffer Full pins (R

x0BF and Rx1BF) can be

used to indicate that a valid message has been loaded

into RXB0 or RXB1, respectively. The pins have three

different configurations (see Tab le 3- 1):

1. Disabled

2. Buffer Full Interrupt

3. Digital Output

3.7.4.1 Disabled

The RxnBF pins can be disabled to the high-

impedance state by clearing the BxBFE bit in the

BFPCTRL register.

3.7.4.2 Configured as Buffer Full

The RxnBF pins can be configured to act as either

buffer full interrupt pins or as standard digital outputs.

Configuration and status of these pins is available via

the BFPCTRL register (Register 4-11). When set to

operate in Interrupt mode (by setting the BxBFE and

BxBFM bits in the BFPCTRL register), these pins are

active-low and are mapped to the RXxIF bit in the

CANINTF register for each receive buffer. When this bit

goes high for one of the receive buffers (indicating that

a valid message has been loaded into the buffer), the

corresponding R

xnBF pin will go low. When the RXxIF

bit is cleared by the MCU, the corresponding interrupt

pin will go to the logic-high state until the next message

is loaded into the receive buffer.

FIGURE 3-5: START-OF-FRAME SIGNALING

START-OF-FRAME BIT

Sample

Point

ID BIT

RxCAN

SOF

EXPECTED START-OF-FRAME BIT

Sample

Point

BUS IDLE

RxCAN

SOF

Expected

Normal SOF Signaling

Glitch Filtering

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