nRF52810产品规范：蓝牙5.0芯片与智能设备应用

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"nRF52810_PS_v1.3.pdf是nordic公司nRF52810芯片的产品规格书，该芯片适用于智能手环等设备，支持蓝牙5.0技术。" nRF52810是一款由Nordic Semiconductor设计的高性能、低功耗的2.4GHz无线收发器，专为蓝牙低能量（Bluetooth Low Energy, BLE）应用而优化。这款芯片集成了许多关键功能，使其在物联网(IoT)设备和可穿戴技术中广泛应用。其主要特性包括： 1. **2.4GHz收发器**：nRF52810支持蓝牙5.0协议，提供-96dBm的接收灵敏度，确保了在复杂射频环境中的稳定通信。 2. **数据速率**：支持1Mbps和2Mbps的数据传输速率，以适应不同应用场景的需求。 3. **发射功率**：可在-20到+4dBm范围内以4dB步进进行配置，提供了广泛的覆盖范围选择。 4. **单端 balun 设计**：集成的balun减少了外部组件需求，简化了电路设计。 5. **低功耗性能**：在传输（TX）和接收（RX）模式下峰值电流分别为4.6mA，有助于延长电池寿命。 6. **RSSI功能**：具有1dB分辨率的接收信号强度指示器，用于评估链路质量。 7. **处理器核心**：基于ARM Cortex-M4的32位处理器，工作频率可达64MHz，提供144EEMB CoreMark分数，性能强大。 8. **能效比**：在Flash和RAM中运行CoreMark时，功耗分别为34.4µA/MHz和32.8µA/MHz，体现其高效能源管理。 9. **调试接口**：支持串行线调试（SWD），方便开发和故障排查。 10. **电源管理**：灵活的电源管理系统，1.7V至3.6V供电范围，内置LDO和DC/DC调节器。 11. **快速唤醒**：利用64MHz内部振荡器实现快速唤醒功能。 12. **低功耗模式**：在不同系统关闭模式下，芯片能保持极低的待机电流，例如在System OFF模式下，无RAM保留时仅为0.3µA，而在有全24kBRAM保留时则为0.5µA。 13. **RTC唤醒**：在System ON模式下，带有24kBRAM保留，且由RTC唤醒时，电流消耗为1.5µA；无RAM保留时，仅RTC唤醒的电流消耗为1.4µA。 14. **内存配置**：配备192kB的闪存和24kB的RAM，满足应用程序的存储需求。 15. **软设备就绪**：意味着它兼容Nordic的SoftDevice软件栈，简化了多协议并发支持。 16. **12位ADC**：具有200ksps采样率的8通道ADC，适用于传感器数据采集。 nRF52810是一款功能全面、功耗极低的微控制器，特别适合对性能和电池寿命有高要求的蓝牙5.0物联网和可穿戴设备应用。其强大的处理能力、灵活的电源管理以及优秀的射频性能，使其成为设计者们理想的选型之一。

Core components

4.1 CPU

The ARM

Cortex-M4 processor has a 32-bit instruction set (Thumb

-2 technology) that implements a

superset of 16- and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance

signal processing including:

• Digital signal processing (DSP) instructions

• Single-cycle multiply and accumulate (MAC) instructions

• Hardware divide

• 8 and 16-bit single instruction multiple data (SIMD) instructions

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the

ARM Cortex processor series is implemented and available for the M4 CPU.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling

events at configurable priority levels via the nested vectored interrupt controller (NVIC).

Executing code from flash will have a wait state penalty on the nRF52 Series. The section Electrical

specification on page 16 shows CPU performance parameters including wait states in different modes,

CPU current and efficiency, and processing power and efficiency based on the CoreMark

benchmark.

The ARM System Timer (SysTick) is present on the device. The SysTick's clock will only tick when the CPU is

running or when the system is in debug interface mode.

4.1.1 Electrical specification

4.1.1.1 CPU performance

The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is

executing the CoreMark

benchmark. It includes power regulator and clock base currents. All other blocks

are IDLE.

Symbol Description Min. Typ. Max. Units

FLASH

CPU wait states, running from flash 0 2

RAM

CPU wait states, running from RAM 0

FLASH

CoreMark

, running from flash

144 CoreMark

FLASH/MHz

CoreMark per MHz, running from flash 2.25 CoreMark/

MHz

FLASH/mA

CoreMark per mA, running from flash, DCDC 3V 65 CoreMark/

4.1.2 CPU and support module configuration

The ARM

Cortex

-M4 processor has a number of CPU options and support modules implemented on the

device.

Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs --

no_size_constraints

4430_161 v1.3

Core components

0x20000000

0x20001000

0x20002000

0x20003000

0x20004000

0x20005000

RAM2

AHB slave

RAM1

AHB slave

RAM0

AHB slave

Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

AHB multilayer interconnect

Data RAM

System

AHB

slave

Page 0

Page 1

Page 2

Page 3..46

Page 47

0x00000000

0x00002000

0x00003000

0x0002F000

Flash

ICODE/DCODE

AHB

slave

NVMC

ICODE

DCODE

0x00800000

0x00801000

0x00802000

0x00803000

0x00804000

0x00805000

Code RAM

ICODE/DCODE

Peripheral

EasyDMA

DMA bus

Peripheral

EasyDMA

DMA bus

CPU

ARM Cortex-M4

System bus

ICODE

DCODE

AHB2APB

AHB

APB

Block 0

Block 1

Block 2..6

Block 7

0x00000200

0x00000400

0x00001000

0x00000E00

Figure 2: Memory layout

See AHB multilayer on page 38 and EasyDMA on page 36 for more information about the AHB

multilayer interconnect and the EasyDMA.

The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the

application to partition the RAM within these regions so that one does not corrupt the other.

4.2.1 RAM - Random access memory

The RAM interface is divided into multiple RAM AHB slaves.

Each RAM AHB slave is connected to two 4-kilobyte RAM sections, see Section 0 and Section 1 in Memory

layout on page 18.

Each of the RAM sections have separate power control for System ON and System OFF mode operation,

which is configured via RAM register (see the POWER — Power supply on page 49).

4.2.2 Flash - Non-volatile memory

The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of

times it can be written and erased, and also on how it can be written.

Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile

memory controller on page 20.

The flash is divided into multiple 4 kB pages that can be accessed by the CPU via both the ICODE and

DCODE buses as shown in, Memory layout on page 18. Each page is divided into 8 blocks.

4.2.3 Memory map

The complete memory map is shown in Memory map on page 19. As described in Memory on page

17, Code RAM and Data RAM are the same physical RAM.

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Core components

ID Base address Peripheral Instance Description

18 0x40012000 QDEC QDEC Quadrature decoder

19 0x40013000 COMP COMP General purpose comparator

20 0x40014000 EGU EGU0 Event generator unit 0

20 0x40014000 SWI SWI0 Software interrupt 0

21 0x40015000 EGU EGU1 Event generator unit 1

21 0x40015000 SWI SWI1 Software interrupt 1

22 0x40016000 SWI SWI2 Software interrupt 2

23 0x40017000 SWI SWI3 Software interrupt 3

24 0x40018000 SWI SWI4 Software interrupt 4

25 0x40019000 SWI SWI5 Software interrupt 5

28 0x4001C000 PWM PWM0 Pulse-width modulation unit 0

29 0x4001D000 PDM PDM Pulse-density modulation (digital microphone interface)

30 0x4001E000 NVMC NVMC Non-volatile memory controller

31 0x4001F000 PPI PPI Programmable peripheral interconnect

N/A 0x10000000 FICR FICR Factory information configuration

N/A 0x10001000 UICR UICR User information configuration

Table 4: Instantiation table

4.3 NVMC — Non-volatile memory controller

The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory

and the UICR (user information configuration registers).

The CONFIG on page 22 is used to enable the NVMC for writing (CONFIG.WEN) and erasing

(CONFIG.EEN). The user must make sure that writing and erasing are not enabled at the same time. Having

both enabled at the same time may result in unpredictable behavior.

The CPU must be halted before initiating a NVMC operation from the debug system.

4.3.1 Writing to flash

When writing is enabled, full 32-bit words are written to word-aligned addresses in flash.

As illustrated in Memory on page 17, the flash is divided into multiple pages. The same 32-bit word in

the flash can only be written n

WRITE

number of times before a page erase must be performed.

The NVMC is only able to write 0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit back

to 1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,

write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1.

Note that the restriction on the number of writes (n

WRITE

) still applies in this case.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

The time it takes to write a word to flash is specified by t

WRITE

. The CPU is halted while the NVMC is writing

to the flash.

4.3.2 Erasing a page in flash

When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page

22.

After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified

by t

ERASEPAGE

. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the

flash.

See Partial erase of a page in flash on page 21 for information on dividing the page erase time into

shorter chunks.

4430_161 v1.3

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