9
DS90UB913A-Q1
www.ti.com.cn
ZHCSEW6F –MAY 2013–REVISED JANUARY 2020
Copyright © 2013–2020, Texas Instruments Incorporated
Electrical Characteristics
(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
GPO
Pin Capacitance GPO [3:0] 1.5 pF
LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
V
IH
High Level Input
Voltage
V
IN
= 1.71 V to 1.89 V 0.65 V
IN
V
IN
V
V
IL
Low Level Input
Voltage
V
IN
= 1.71 V to 1.89 V GND 0.35 V
IN
I
IN
Input Current V
IN
= 0 V or 1.89 V, V
IN
= 1.71 V to 1.89 V –20 ±1 20 µA
V
OH
High Level Output
Voltage
V
DDIO
= 1.71 V to 1.89 V, I
OH
= −4 mA V
DDIO
- 0.45 V
DDIO
V
V
OL
Low Level Output
Voltage
V
DDIO
= 1.71 V to 1.89 V I
OL
= 4 mA GND 0.45 V
I
OS
Output Short Circuit
Current
V
OUT
= 0 V
Serializer
GPO Outputs
–11 mA
I
OZ
TRI-STATE Output
Current
PDB = 0 V,
V
OUT
= 0 V or V
DDIO
Serializer
GPO Outputs
-20 20 µA
C
GPO
Pin Capacitance GPO [3:0] 1.5 pF
I
IN-STRAP
Strap pin input current V
IN
= 0 V to V
DD_n
-1 1 µA
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
V
IH
High Level Input
Voltage
V
IN
= 2.52 V to 3.08 V 0.7 V
IN
V
IN
V
V
IL
Low Level Input
Voltage
V
IN
= 2.52 V to 3.08 V GND 0.3 V
IN
I
IN
Input Current V
IN
= 0 V or 3.08 V, V
IN
= 2.52 V to 3.08 V –20 ±1 20 µA
V
OH
High Level Output
Voltage
V
DDIO
= 2.52 V to 3.08 V, I
OH
= −4 mA V
DDIO
- 0.4 V
DDIO
V
V
OL
Low Level Output
Voltage
V
DDIO
=2.52 V to 3.08V I
OL
= 4 mA GND 0.4 V
I
OS
Output Short Circuit
Current
V
OUT
= 0 V
Serializer
GPO Outputs
–11 mA
I
OZ
TRI-STATE Output
Current
PDB = 0 V,
V
OUT
= 0 V or V
DDIO
Serializer
GPO Outputs
–20 20 µA
C
GPO
Pin Capacitance GPO [3:0] 1.5 pF
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
V
OD
Differential Output
Voltage
R
L
= 100 Ω (Figure 6), Back Channel Disabled 640 824
mV
V
OUT
Single-Ended Output
Voltage
R
L
= 50 Ω (Figure 6), Back Channel Disabled 320 412
ΔV
OD
Differential Output
Voltage Unbalance
R
L
= 100 Ω 1 50 mV
V
OS
Output Offset Voltage R
L
= 100 Ω (Figure 6)
V
DD_n
-
V
OD/2
V
ΔV
OS
Offset Voltage
Unbalance
R
L
= 100 Ω 1 50 mV
I
OS
Output Short Circuit
Current
DOUT+ = 0 V or DOUT– = 0 V –26 mA
R
T
Differential Internal
Termination
Resistance
Differential across DOUT+ and DOUT– 80 100 120
Ω
Single-ended
Termination
Resistance
DOUT+ or DOUT– 40 50 60
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