Marvell Alaska 88E1512 芯片数据手册

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"88E1512芯片手册详细技术文档" Marvell的Alaska系列88E1512是一款高度集成的10/100/1000Mbps能源高效以太网收发器，专为满足现代网络设备对高速、低能耗的需求而设计。该芯片手册提供了全面的技术规格、功能描述、接口信息以及应用指南，旨在帮助工程师们更好地理解和应用88E1512。 88E1512的主要特性包括： 1. **能源效率**：88E1512支持能源高效以太网（Energy Efficient Ethernet, EEE）标准，能够在低数据传输时降低功耗，从而减少整体网络的运行成本。 2. **多速率支持**：芯片支持10/100/1000Mbps三种速度等级，适应不同的网络环境需求。 3. **高级功能**：包括自动协商（Auto-Negotiation）、介质独立接口（MII/RMII/GMII/MIX接口）、端口聚合（Link Aggregation Control Protocol, LACP）以及错误检测和校正机制等。 4. **接口兼容性**：88E1512能够与多种网络处理器或CPU接口无缝配合，提供灵活的系统设计选择。 5. **物理层(PHY)功能**：具备包括自适应均衡、接收均衡、回声消除、线缆诊断和故障检测等功能，确保数据传输的稳定性和可靠性。 6. **安全性**：可能包含硬件支持的加密和认证功能，如IEEE 802.1AE MACSec，以增强网络数据的安全性。 7. **环境适应性**：适应广泛的温度范围和电源电压，适用于多种工业和商业环境。在手册中，开发者可以找到以下关键信息： - **电气特性**：包括电源电压、电流消耗、输入/输出信号电平等参数，对于硬件设计至关重要。 - **封装和引脚定义**：详细列出了88E1512的不同封装类型及其引脚功能，方便PCB布局和焊接。 - **操作模式**：描述了芯片在不同网络配置下的工作模式，如全双工、半双工、单工等。 - **测试条件和性能指标**：提供了实验室测试的数据，以验证芯片的性能表现。 - **故障排查和诊断**：包含故障状态指示和诊断工具，帮助快速定位并解决问题。此外，Marvell公司提醒，本手册内容仅供参考，不提供任何明示或暗示的保修。使用者在实际应用中应根据具体情况进行调整，并且遵循Marvell的更新文档，以获取最新的技术信息和更改。访问Marvell的官方网站（http://www.marvell.com）可获取更多详细信息，包括最新的产品更新、软件开发工具和支持文档，以便进行更深入的学习和应用。

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 16 Document Classification: Public February 23, 2018

Figure 34: MDC/MDIO Timing ........................................................................................................................138

Figure 35: ........................................................................................................................................................139

Figure 36: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing ........................................................140

Figure 37: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................141

Figure 38: 10/100/1000BASE-T to SGMII Latency Timing ..............................................................................142

Figure 39: SGMII to 10/100/1000BASE-T Latency Timing ..............................................................................142

5 Package Mechanical Dimensions .................................................................................................143

Figure 40: 88E1510/88E1518 48-pin QFN Package Mechanical Drawings ....................................................143

Figure 41: 88E1512/88E1514 56-pin QFN Package Mechanical Drawings ....................................................145

6 Part Order Numbering/Package Marking......................................................................................147

Figure 42: Sample Part Number ......................................................................................................................147

Figure 43: 88E1510 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................149

Figure 44: 88E1518 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 45: 88E1512 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 46: 88E1514 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................151

Figure 47: 88E1510 48-pin QFN Industrial Package Marking and Pin 1 Location...........................................151

Figure 48: 88E1512 56-pin QFN Industrial Package Marking and Pin 1 Location...........................................152

A Revision History .............................................................................................................................153

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 20 Document Classification: Public February 23, 2018

The RGMII supports 10/100/1000BASE-T modes of operation.

Table 4: RGMII

48-QFN

Pin #

Pin Name Pin

Type

Description

47 TX_CLK I RGMII Transmit Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance depending on speed.

2 TX_CTRL I RGMII Transmit Control. TX_EN is presented on the rising edge of TX_CLK.

A logical derivative of TX_EN and TX_ER is presented on the falling edge of

TX_CLK.

TXD[3]

TXD[2]

TXD[1]

TXD[0]

I RGMII Transmit Data.

TXD[3:0] run at double data rate with bits [3:0] of each byte to be transmitted

on the rising edge of TX_CLK, and bits [7:4] presented on the falling edge of

TX_CLK.

In 10/100BASE-T modes, the transmit data nibble is presented on TXD[3:0] on

the rising edge of TX_CLK.

40 RX_CLK O RGMII Receive Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance derived from the received data stream

depending on speed.

37 RX_CTRL O RGMII Receive Control. RX_DV is presented on the rising edge of RX_CLK.

A logical derivative of RX_DV and RX_ER is presented on the falling edge of

RX_CLK.

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O RGMII Receive Data. RXD[3:0] run at double data rate with bits [3:0] of each

byte received on the rising edge of RX_CLK, and bits [7:4] presented on the

falling edge of RX_CLK.

In 10/100BASE-T modes, the receive data nibble is presented on RXD[3:0] on

the rising edge of RX_CLK.

Table 5: Management Interface and Interrupt

48-QFN

Pin #

Pin Name Pin

Type

Description

4 MDC I MDC is the management data clock reference for the serial management

interface. A continuous clock stream is not expected. The maximum frequency

supported is 12 MHz.

5 MDIO I/O MDIO is the management data. MDIO transfers management data in and out of

the device synchronously to MDC. This pin requires a pull-up resistor in a

range from 1.5 kΩ to 10 kΩ.

Table 6: LED Interface

48-QFN

Pin #

Pin Name Pin

Type

Description

10 LED[0] O LED output.

9 LED[1] I/O LED output

8 LED[2]/INTn O LED/Interrupt outputs.

LED[2] pin also functions as an active low interrupt pin.

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