Spartan-3E FPGA: 低成本高效能解决方案

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“Spartan-3E是Xilinx公司的一款基于90纳米工艺技术的现场可编程门阵列（FPGA）系列，旨在提供更高的性价比和功能带宽。这款芯片家族在原有的Spartan-3基础上增加了每个I/O端口的逻辑量，降低了每个逻辑单元的成本，同时引入了新特性以提升系统性能并降低配置成本。Spartan-3E适用于各种消费电子应用，如宽带接入、家庭网络、显示/投影和数字电视设备。” Spartan-3E FPGA的关键知识点包括： 1. **架构概述**：Spartan-3E家族采用先进的90纳米工艺技术，这使得它们能够在更小的封装内集成更多的逻辑功能，同时降低了功耗。这种技术进步使得芯片能够提供比以往更高的性价比。 2. **输入/输出块（IOBs）**：Spartan-3E的IOBs是其关键组成部分，它们支持多种信号标准，如SelectIO™技术，这允许用户根据应用需求灵活配置输入/输出信号标准。 3. **可配置逻辑块（CLB）**：CLB是FPGA内部的基本逻辑构建模块，可以配置成实现用户所需的任意逻辑函数。Spartan-3E的CLB设计提升了逻辑密度，增强了灵活性。 4. **块RAM**：Spartan-3E包含内置的BlockRAM资源，可用于实现高速数据存储和内存功能，这对于处理实时数据处理和存储要求的应用至关重要。 5. **专用乘法器**：这些硬件乘法器加速了乘法操作，提高了计算密集型算法的执行速度。 6. **数字时钟管理器（DCM）**：DCM负责生成、分频和相位调整时钟信号，有助于管理和优化系统时钟的性能，减少时钟抖动并提高系统稳定性。 7. **时钟网络**：时钟网络在FPGA中起着至关重要的作用，确保数据同步和正确操作。Spartan-3E的时钟网络设计优化了时钟分布和时钟延迟，有助于提高系统性能。 8. **配置**：Spartan-3E FPGA的配置过程涉及加载编程数据以定义其逻辑功能。这一过程可以通过外部存储器或嵌入式配置器件来完成。 9. **供电**：Spartan-3E FPGA需要正确的电源电压来保证正常工作，因此设计者必须根据器件规格提供适当的电源管理。 10. **生产步进**：生产步进是指在芯片制造过程中不同批次的微小差异，这些差异可能影响性能和可靠性。了解生产步进信息对于选择适合特定应用的器件至关重要。 11. **直流和开关特性**：这部分涵盖了芯片的电气特性，如直流电气特性、绝对最大额定值、电源电压规格等，这些都是设计电路板时需要考虑的重要参数，以确保器件在预期的工作条件下可靠运行。 Spartan-3E FPGA通过其创新的架构和丰富的功能集，为消费电子产品提供了经济高效的解决方案，实现了高性价比的系统设计。无论是对成本敏感的家用电器还是高性能的数字设备，Spartan-3E都能提供合适的平台来满足设计需求。

Spartan-3 FPGA Family: Functional Description

DS312 (4.0) October 29, 2012 www.xilinx.com

Product Specification 16

PRODUCT NOT RECOMMENDED FOR NEW DESIGNS

HSTL and SSTL inputs use the Reference Voltage (V

REF

) to

bias the input-switching threshold. Once a configuration

data file is loaded into the FPGA that calls for the I/Os of a

given bank to use HSTL/SSTL, a few specifically reserved

I/O pins on the same bank automatically convert to V

REF

inputs. For banks that do not contain HSTL or SSTL, V

REF

pins remain available for user I/Os or input pins.

Differential standards employ a pair of signals, one the

opposite polarity of the other. The noise canceling

properties (for example, Common-Mode Rejection) of these

standards permit exceptionally high data transfer rates. This

subsection introduces the differential signaling capabilities

of Spartan-3E devices.

Each device-package combination designates specific I/O

pairs specially optimized to support differential standards. A

unique L-number, part of the pin name, identifies the

line-pairs associated with each bank (see Module 4, Pinout

Descriptions). For each pair, the letters P and N designate

the true and inverted lines, respectively. For example, the

pin names IO_L43P_3 and IO_L43N_3 indicate the true

and inverted lines comprising the line pair L43 on Bank 3.

CCO

provides current to the outputs and additionally

powers the On-Chip Differential Termination. V

CCO

must be

2.5V when using the On-Chip Differential Termination. The

REF

lines are not required for differential operation.

To further understand how to combine multiple

IOSTANDARDs within a bank, refer to IOBs Organized into

Banks, page 18.

On-Chip Differential Termination

Spartan-3E devices provide an on-chip ~120Ω differential

termination across the input differential receiver terminals.

The on-chip input differential termination in Spartan-3E

devices potentially eliminates the external 100Ω termination

resistor commonly found in differential receiver circuits.

Differential termination is used for LVDS, mini-LVDS, and

RSDS as applications permit.

On-chip Differential Termination is available in banks with

CCO

= 2.5V and is not supported on dedicated input pins.

Set the DIFF_TERM attribute to TRUE to enable Differential

Termination on a differential I/O pin pair.

The DIFF_TERM attribute uses the following syntax in the

UCF file:

INST <I/O_BUFFER_INSTANTIATION_NAME>

DIFF_TERM = "<TRUE/FALSE>";

Tabl e 7 : Differential IOSTANDARD Bank Compatibility

Differential

IOSTANDARD

CCO

Supply Input

Requirements:

REF

Differential Bank

Restriction

(1)

1.8V 2.5V 3.3V

LVDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

REF

is not used for

these I/O standards

Applies to Outputs

Only

RSDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

Applies to Outputs

Only

MINI_LVDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

Applies to Outputs

Only

LVPECL_25 Input Input Input

No Differential Bank

Restriction

(other I/O bank

restrictions might

apply)

BLVDS_25 Input

Input,

Output

Input

DIFF_HSTL_I_18

Input,

Output

Input Input

DIFF_HSTL_III_18

Input,

Output

Input Input

DIFF_SSTL18_I

Input,

Output

Input Input

DIFF_SSTL2_I Input

Input,

Output

Input

Notes:

1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.

Spartan-3 FPGA Family: Functional Description

DS312 (4.0) October 29, 2012 www.xilinx.com

Product Specification 17

PRODUCT NOT RECOMMENDED FOR NEW DESIGNS

Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors inside each IOB optionally

force a floating I/O or Input-only pin to a determined state.

Pull-up and pull-down resistors are commonly applied to

unused I/Os, inputs, and three-state outputs, but can be

used on any I/O or Input-only pin. The pull-up resistor

connects an IOB to V

CCO

through a resistor. The resistance

value depends on the V

CCO

voltage (see Module 3, DC and

Switching Characteristics for the specifications). The

pull-down resistor similarly connects an IOB to ground with

a resistor. The PULLUP and PULLDOWN attributes and

library primitives turn on these optional resistors.

By default, PULLDOWN resistors terminate all unused I/O

and Input-only pins. Unused I/O and Input-only pins can

alternatively be set to PULLUP or FLOAT. To change the

unused I/O Pad setting, set the Bitstream Generator

(BitGen) option UnusedPin to PULLUP, PULLDOWN, or

FLOAT. The UnusedPin option is accessed through the

Properties for Generate Programming File in ISE. See

Bitstream Generator (BitGen) Options.

During configuration a Low logic level on the HSWAP pin

activates pull-up resistors on all I/O and Input-only pins not

actively used in the selected configuration mode.

Keeper Circuit

Each I/O has an optional keeper circuit (see Figure 12) that

keeps bus lines from floating when not being actively driven.

The KEEPER circuit retains the last logic level on a line after

all drivers have been turned off. Apply the KEEPER

attribute or use the KEEPER library primitive to use the

KEEPER circuitry. Pull-up and pull-down resistors override

the KEEPER settings.

Slew Rate Control and Drive Strength

Each IOB has a slew-rate control that sets the output

switching edge-rate for LVCMOS and LVTTL outputs. The

SLEW attribute controls the slew rate and can either be set

to SLOW (default) or FAST.

Each LVCMOS and LVTTL output additionally supports up

to six different drive current strengths as shown in Tabl e 8.

To adjust the drive strength for each output, the DRIVE

attribute is set to the desired drive strength: 2, 4, 6, 8, 12,

and 16. Unless otherwise specified in the FPGA application,

the software default IOSTANDARD is LVCMOS25, SLOW

slew rate, and 12 mA output drive.

High output current drive strength and FAST output slew

rates generally result in fastest I/O performance. However,

these same settings generally also result in transmission

line effects on the printed circuit board (PCB) for all but the

shortest board traces. Each IOB has independent slew rate

and drive strength controls. Use the slowest slew rate and

lowest output drive current that meets the performance

requirements for the end application.

Likewise, due to lead inductance, a given package supports

a limited number of simultaneous switching outputs (SSOs)

when using fast, high-drive outputs. Only use fast,

high-drive outputs when required by the application.

X-Ref Target - Figure 11

Figure 11: Differential Inputs and Outputs

100Ω

~120Ω

Spartan-3E

Differential Input

= 50Ω

Spartan-3E

Differential

Output

Spartan-3E

Differential Input

with On-Chip

Differential

Terminator

= 50Ω

Spartan-3E

Differential

Output

DS312-2_24_082605

X-Ref Target - Figure 12

Figure 12: Keeper Circuit

Tabl e 8: Programmable Output Drive Current

IOSTANDARD

Output Drive Current (mA)

2 4 6 8 12 16

LVT TL ✔✔✔✔✔✔

LVC MOS 33 ✔✔✔✔✔✔

LVC MOS 25 ✔✔✔✔✔

LVC MOS 18 ✔✔✔✔ - -

LVC MOS 15 ✔✔✔ - - -

LVC MOS 12 ✔

- - - - -

Pull-up

Pull-down

Input Path

Output Path

Keeper

DS312-2_25_020807

Spartan-3 FPGA Family: Functional Description

DS312 (4.0) October 29, 2012 www.xilinx.com

Product Specification 18

PRODUCT NOT RECOMMENDED FOR NEW DESIGNS

IOBs Organized into Banks

The Spartan-3E architecture organizes IOBs into four I/O

banks as shown in Figure 13. Each bank maintains

separate V

CCO

and V

REF

supplies. The separate supplies

allow each bank to independently set V

CCO

. Similarly, the

REF

supplies can be set for each bank. Refer to Ta bl e 6

and Tab l e 7 for V

CCO

and V

REF

requirements.

When working with Spartan-3E devices, most of the

differential I/O standards are compatible and can be

combined within any given bank. Each bank can support

any two of the following differential standards: LVDS_25

outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As

an example, LVDS_25 outputs, RSDS_25 outputs, and any

other differential inputs while using on-chip differential

termination are a valid combination. A combination not

allowed is a single bank with LVDS_25 outputs, RSDS_25

outputs, and MINI_LVDS_25 outputs.

I/O Banking Rules

When assigning I/Os to banks, these V

CCO

rules must be

followed:

1. All V

CCO

pins on the FPGA must be connected even if a

bank is unused.

2. All V

CCO

lines associated within a bank must be set to

the same voltage level.

3. The V

CCO

levels used by all standards assigned to the

I/Os of any given bank must agree. The Xilinx

development software checks for this. Ta bl e 6 and

Tabl e 7 describe how different standards use the V

CCO

supply.

4. If a bank does not have any V

CCO

requirements,

connect V

CCO

to an available voltage, such as 2.5V or

3.3V. Some configuration modes might place additional

CCO

requirements. Refer to Configuration for more

information.

If any of the standards assigned to the Inputs of the bank

use V

REF

, then the following additional rules must be

observed:

1. All V

REF

pins must be connected within a bank.

2. All V

REF

lines associated with the bank must be set to

the same voltage level.

3. The V

REF

levels used by all standards assigned to the

Inputs of the bank must agree. The Xilinx development

software checks for this. Ta bl e 6 describes how different

standards use the V

REF

supply.

If V

REF

is not required to bias the input switching thresholds,

all associated V

REF

pins within the bank can be used as

user I/Os or input pins.

Package Footprint Compatibility

Sometimes, applications outgrow the logic capacity of a

specific Spartan-3E FPGA. Fortunately, the Spartan-3E

family is designed so that multiple part types are available in

pin-compatible package footprints, as described in

Module 4, Pinout Descriptions. In some cases, there are

subtle differences between devices available in the same

footprint. These differences are outlined for each package,

such as pins that are unconnected on one device but

connected on another in the same package or pins that are

dedicated inputs on one package but full I/O on another.

When designing the printed circuit board (PCB), plan for

potential future upgrades and package migration.

The Spartan-3E family is not pin-compatible with any

previous Xilinx FPGA family.

Dedicated Inputs

Dedicated Inputs are IOBs used only as inputs. Pin names

designate a Dedicated Input if the name starts with IP, for

example, IP or IP_Lxxx_x. Dedicated inputs retain the full

functionality of the IOB for input functions with a single

exception for differential inputs (IP_Lxxx_x). For the

differential Dedicated Inputs, the on-chip differential

termination is not available. To replace the on-chip

differential termination, choose a differential pair that

supports outputs (IO_Lxxx_x) or use an external 100Ω

termination resistor on the board.

ESD Protection

Clamp diodes protect all device pads against damage from

Electro-Static Discharge (ESD) as well as excessive voltage

transients. Each I/O has two clamp diodes: one diode

extends P-to-N from the pad to V

CCO

and a second diode

extends N-to-P from the pad to GND. During operation,

these diodes are normally biased in the off state. These

clamp diodes are always connected to the pad, regardless

of the signal standard selected. The presence of diodes

limits the ability of Spartan-3E I/Os to tolerate high signal

voltages. The V

absolute maximum rating in Table 7 3 of

Module 3, DC and Switching Characteristics specifies the

voltage range that I/Os can tolerate.

X-Ref Target - Figure 13

Figure 13: Spartan-3E I/O Banks (top view)

DS312-2_26_021205

Bank 0

Bank 2

Bank 3

Bank 1

Spartan-3 FPGA Family: Functional Description

DS312 (4.0) October 29, 2012 www.xilinx.com

Product Specification 19

PRODUCT NOT RECOMMENDED FOR NEW DESIGNS

Supply Voltages for the IOBs

The IOBs are powered by three supplies:

1. The V

CCO

supplies, one for each of the FPGA’s I/O

banks, power the output drivers. The voltage on the

CCO

pins determines the voltage swing of the output

signal.

2. V

CCINT

is the main power supply for the FPGA’s internal

logic.

3. V

CCAUX

is an auxiliary source of power, primarily to

optimize the performance of various FPGA functions

such as I/O switching.

I/O and Input-Only Pin Behavior During

Power-On, Configuration, and User Mode

In this section, all behavior described for I/O pins also

applies to input-only pins and dual-purpose I/O pins that are

not actively involved in the currently-selected configuration

mode.

All I/O pins have ESD clamp diodes to their respective V

CCO

supply and from GND, as shown in Figure 5. The V

CCINT

(1.2V), V

CCAUX

(2.5V), and V

CCO

supplies can be applied in

any order. Before the FPGA can start its configuration

process, V

CCINT

, V

CCO

Bank 2, and V

CCAUX

must have

reached their respective minimum recommended operating

levels indicated in Ta bl e 7 4. At this time, all output drivers

are in a high-impedance state. V

CCO

Bank 2, V

CCINT

, and

CCAUX

serve as inputs to the internal Power-On Reset

circuit (POR).

A Low level applied to the HSWAP input enables pull-up

resistors on user-I/O and input-only pins from power-on

throughout configuration. A High level on HSWAP disables

the pull-up resistors, allowing the I/Os to float. HSWAP

contains an internal pull-up resistor and defaults to High if

left floating. As soon as power is applied, the FPGA begins

initializing its configuration memory. At the same time, the

FPGA internally asserts the Global Set-Reset (GSR), which

asynchronously resets all IOB storage elements to a default

Low state. Also see Pin Behavior During Configuration.

Upon the completion of initialization and the beginning of

configuration, INIT_B goes High, sampling the M0, M1, and

M2 inputs to determine the configuration mode.

Configuration data is then loaded into the FPGA. The I/O

drivers remain in a high-impedance state (with or without

pull-up resistors, as determined by the HSWAP input)

throughout configuration.

At the end of configuration, the GSR net is released, placing

the IOB registers in a Low state by default, unless the

loaded design reverses the polarity of their respective SR

inputs.

The Global Three State (GTS) net is released during

Start-Up, marking the end of configuration and the

beginning of design operation in the User mode. After the

GTS net is released, all user I/Os go active while all unused

I/Os are pulled down (PULLDOWN). The designer can

control how the unused I/Os are terminated after GTS is

released by setting the Bitstream Generator (BitGen) option

UnusedPin to PULLUP, PULLDOWN, or FLOAT.

One clock cycle later (default), the Global Write Enable

(GWE) net is released allowing the RAM and registers to

change states. Once in User mode, any pull-up resistors

enabled by HSWAP revert to the user settings and HSWAP

is available as a general-purpose I/O. For more information

on PULLUP and PULLDOWN, see Pull-Up and Pull-Down

Resistors.

Behavior of Unused I/O Pins After

Configuration

By default, the Xilinx ISE development software

automatically configures all unused I/O pins as input pins

with individual internal pull-down resistors to GND.

This default behavior is controlled by the UnusedPin

bitstream generator (BitGen) option, as described in

Tabl e 69.

JTAG Boundary-Scan Capability

All Spartan-3E IOBs support boundary-scan testing

compatible with IEEE 1149.1/1532 standards. During

boundary-scan operations such as EXTEST and HIGHZ the

pull-down resistor is active. See JTAG Mode for more

information on programming via JTAG.

Spartan-3 FPGA Family: Functional Description

DS312 (4.0) October 29, 2012 www.xilinx.com

Product Specification 20

PRODUCT NOT RECOMMENDED FOR NEW DESIGNS

Configurable Logic Block (CLB) and

Slice Resources

For additional information, refer to the “Using Configurable

Logic Blocks (CLBs)” chapter in UG331

CLB Overview

The Configurable Logic Blocks (CLBs) constitute the main

logic resource for implementing synchronous as well as

combinatorial circuits. Each CLB contains four slices, and

each slice contains two Look-Up Tables (LUTs) to

implement logic and two dedicated storage elements that

can be used as flip-flops or latches. The LUTs can be used

as a 16x1 memory (RAM16) or as a 16-bit shift register

(SRL16), and additional multiplexers and carry logic simplify

wide logic and arithmetic functions. Most general-purpose

logic in a design is automatically mapped to the slice

resources in the CLBs. Each CLB is identical, and the

Spartan-3E family CLB structure is identical to that for the

Spartan-3 family.

CLB Array

The CLBs are arranged in a regular array of rows and

columns as shown in Figure 14.

Each density varies by the number of rows and columns of

CLBs (see Tab le 9 ).

Slices

Each CLB comprises four interconnected slices, as shown

in Figure 16. These slices are grouped in pairs. Each pair is

organized as a column with an independent carry chain.

The left pair supports both logic and memory functions and

its slices are called SLICEM. The right pair supports logic

only and its slices are called SLICEL. Therefore half the

LUTs support both logic and memory (including both

RAM16 and SRL16 shift registers) while half support logic

only, and the two types alternate throughout the array

columns. The SLICEL reduces the size of the CLB and

lowers the cost of the device, and can also provide a

performance advantage over the SLICEM.

X-Ref Target - Figure 14

Figure 14: CLB Locations

DS312-2_31_021205

Spartan-3E

FPGA

X0Y1 X1Y1

X0Y0 X1Y0

IOBs

CLB

Slice

X2Y1 X3Y1

X2Y0 X3Y0

X0Y3 X1Y3

X0Y2 X1Y2

X2Y3 X3Y3

X2Y2 X3Y2

Tabl e 9 : Spartan-3E CLB Resources

Device

CLB

Rows

CLB

Columns

CLB

Total

(1)

Slices

LUTs /

Flip-Flops

Equivalent

Logic Cells

RAM16 /

SRL16

Distributed

RAM Bits

XC3S100E 22 16 240 960 1,920 2,160 960 15,360

XC3S250E 34 26 612 2,448 4,896 5,508 2,448 39,168

XC3S500E 46 34 1,164 4,656 9,312 10,476 4,656 74,496

XC3S1200E 60 46 2,168 8,672 17,344 19,512 8,672 138,752

XC3S1600E 76 58 3,688 14,752 29,504 33,192 14,752 236,032

Notes:

1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are

embedded in the array (see Figure 1 in Module 1).

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