Freescale i.MX6 处理器技术规格解析

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"Freescale i.MX6 数据表提供了该系列处理器的技术详细信息，包括封装、订购信息以及处理器的主要特性和应用。" Freescale i.MX6 系列处理器是面向多媒体应用的高性能、低功耗集成处理器的最新成果。这个系列包括 i.MX6 Dual 和 i.MX6 Quad 两种型号，分别支持双核和四核的 ARM Cortex-A9 处理器。Cortex-A9 核心是 ARM 公司设计的一种高效能、低能耗的微处理器架构，适用于多种嵌入式和移动设备。在 i.MX6 Dual 和 i.MX6 Quad 中，每个核心都能运行到高达 1GHz 的速度，提供了强大的处理能力。它们集成了 2D 和 3D 图形处理器，支持 3D 1080p 视频处理，这使得这些处理器非常适合需要高质量图形和视频的应用，如智能电视、媒体播放器和车载信息系统。此外，i.MX6 系列处理器还配备了 64 位 DDR3/LVDDR3/LPDDR2-1066 内存接口，这为高速数据传输提供了保障，同时支持多种外围设备连接。这些接口可以连接 WLAN、蓝牙、GPS 模块、硬盘、显示器和摄像头传感器等，使得该处理器能够广泛应用于各种物联网(IoT)、汽车电子、工业控制和消费电子产品中。在封装方面，i.MX6 采用 FCBGA 封装，尺寸为 21x21mm，引脚间距为 0.8mm，这种封装技术有利于减小芯片的体积，提高散热性能，同时保持高密度的信号连接。订购信息列出了 MCIMX6QxDxxxxC 和 MCIMX6QxExxxxC 作为 i.MX6 Quad 版本的型号，以及 MCIMX6DxDxxxxC 和 MCIMX6DxExxxxC 作为 i.MX6 Dual 版本的型号，具体的订购代码可能代表不同的配置选项，例如内存大小、功耗等级或温度范围。总体而言，Freescale i.MX6 系列处理器通过其高性能、低功耗的设计，以及丰富的外设接口，展现了在嵌入式计算领域的强大竞争力，广泛应用于需要高效多媒体处理的现代设备中。

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 2.3

16 Freescale Semiconductor

Modules List

uSDHC-1

uSDHC-2

uSDHC-4

SD/MMC and SDXC

Enhanced

Multi-Media Card /

Secure Digital Host

Controller

Connectivity

Peripherals

i.MX 6Dual/6Quad specific SoC characteristics:

All four MMC/SD/SDIO controller IPs are identical and are based on the

uSDHC IP. They are:

• Fully compliant with MMC command/response sets and Physical Layer

as defined in the Multimedia Card System Specification,

v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.

Hardware reset as specified for eMMC cards is supported at ports #3

and #4 only.

• Fully compliant with SD command/response sets and Physical Layer

as defined in the SD Memory Card Specifications, v3.0 including

high-capacity SDHC cards up to 32 GB.

• Fully compliant with SDIO command/response sets and

interrupt/read-wait mode as defined in the SDIO Card Specification,

Part E1, v1.10

• Fully compliant with SD Card Specification, Part A2, SD Host

Controller Standard Specification, v2.00

All four ports support:

• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to

UHS-I SDR104 mode (104 MB/s max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52

MHz in both SDR and DDR modes (104 MB/s max)

However, the SoC-level integration and I/O muxing logic restrict the

functionality to the following:

• Instances #1 and #2 are primarily intended to serve as external slots or

interfaces to on-board SDIO devices. These ports are equipped with

“Card Detection” and “Write Protection” pads and do not support

hardware reset.

• Instances #3 and #4 are primarily intended to serve interfaces to

embedded MMC memory or interfaces to on-board SDIO devices.

These ports do not have “Card detection” and “Write Protection” pads

and do support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There are two completely

independent I/O power domains for Ports #1 and #2 in four bit

configuration (SD interface). Port #3 is placed in his own independent

power domain and port #4 shares power domain with some other

interfaces.

VDOA VDOA Multimedia

Peripherals

The Video Data Order Adapter (VDOA) is used to re-order video data from

the “tiled” order used by the VPU to the conventional raster-scan order

needed by the IPU.

VPU Video Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU), which covers many

SD-level and HD-level video decoders and SD-level encoders as a

multi-standard video codec engine as well as several important video

processing, such as rotation and mirroring.

See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete

list of VPU’s decoding/encoding capabilities.

WDOG-1 Watchdog Timer

Peripherals

The Watchdog Timer supports two comparison points during each

counting period. Each of the comparison points is configurable to evoke

an interrupt to the ARM core, and a second point evokes an external event

on the WDOG line.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

Modules List

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 2.3

Freescale Semiconductor 17

3.1 Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual

(IMX6DQRM). Special signal consideration information is contained in the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

3.2 Recommended Connections for Unused Analog Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused analog

interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of

Applications Processors (IMX6DQ6SDLHDG).

WDOG-2

(TZ)

Watchdog

(TrustZone)

Timer

Peripherals

The TrustZone Watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and

forcing a switch to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such a situation is

undesirable as it can compromise the system’s security. Once the TZ

WDOG module is activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the timer times out. Upon

a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces

switching to the TZ mode. If it is still not served, the TZ WDOG asserts a

security violation signal to the CSU. The TZ WDOG module cannot be

programmed or deactivated by a normal mode Software.

EIM NOR-Flash /PSRAM

interface

Connectivity

Peripherals

The EIM NOR-FLASH / PSRAM provides:

• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and

async operating modes), at slow frequency

• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow

frequency

• Multiple chip selects

XTALOSC Crystal Oscillator

interface

— The XTALOSC module enables connectivity to external crystal oscillator

device. In a typical application use-case, it is used for 24 MHz oscillator.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

Electrical Characteristics

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 2.3

Freescale Semiconductor 19

4.1.2 Thermal Resistance

4.1.2.1 FCPBGA Package Thermal Resistance

Table 5 provides the FCPBGA package thermal resistance data.

MLB I/O supply voltage Supplies denoted as I/O supply -0.3 2.8 V

LVDS I/O supply voltage Supplies denoted as I/O supply -0.3 2.8 V

VDD_HIGH_IN supply voltage VDD_HIGH_IN -0.3 3.6 V

USB VBUS USB_H1_VBUS/USB_OTG_VBUS — 5.25 V

Input voltage on USB_OTG_DP, USB_OTG_DN,

USB_H1_DP, USB_H1_DN pins

USB_DP/USB_DN -0.3 3.63 V

Input/output voltage range V

out

-0.5 OVDD

+0.3 V

ESD damage immunity: V

esd

• Human Body Model (HBM)

• Charge Device Model (CDM)

—

2000

500

Storage temperature range T

STORAGE

-40 150

OVDD is the I/O supply voltage.

Table 5. FCPBGA Package Thermal Resistance Data (Non-Lidded)

Thermal Parameter Test Conditions Symbol Value Unit

Junction to Ambient

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

Single-layer board (1s); natural convection

Per JEDEC JESD51-3 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified

package.

JA

31 C/W

Four-layer board (2s2p); natural convection

JA

22 C/W

Junction to Ambient

Single-layer board (1s); air flow 200 ft/min

Per JEDEC JESD51-6 with the board horizontal.

JMA

24 C/W

Four-layer board (2s2p); air flow 200 ft/min

JMA

18 C/W

Junction to Board

1,4

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

—R

JB

12 C/W

Junction to Case (top)

1,5

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the

interface layer.

—R

JCtop

<0.1 C/W

Table 4. Absolute Maximum Ratings (continued)

Parameter Description Symbol Min Max Unit

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 2.3

20 Freescale Semiconductor

Electrical Characteristics

4.1.3 Operating Ranges

Table 6 provides the operating ranges of the i.MX 6Dual/6Quad processors.

Table 6. Operating Ranges

Parameter

Description

Symbol Min Typ Max

Unit Comment

Run mode: LDO

enabled

VDD_ARM_IN

VDD_ARM23_IN

1.35

— 1.5 V LDO Output Set Point (VDD_ARM_CAP

) of

1.225 V minimum for operation up to 852 MHz

or 996 MHz (depending on the device speed

grade).

1.275

— 1.5 V LDO Output Set Point (VDD_ARM_CAP

) of

1.150 V minimum for operation up to 792 MHz.

1.05

— 1.5 V LDO Output Set Point (VDD_ARM_CAP

) of

0.925 V minimum for operation up to 396 MHz.

VDD_SOC_IN

1.350

3,6

— 1.5 V 264 MHz < VPU  352 MHz; VDDSOC and

VDDPU LDO outputs (VDD_SOC_CAP and

VDD_PU_CAP) require 1.225 V minimum.

1.275

3,6

— 1.5 V VPU  264 MHz; VDDSOC and VDDPU LDO

outputs (VDD_SOC_CAP and VDD_PU_CAP)

require 1.15 V minimum.

Run mode: LDO

bypassed

VDD_ARM_IN

VDD_ARM23_IN

1.225 — 1.3 V LDO bypassed for operation up to 852 MHz or

996 MHz (depending on the device speed

grade).

1.125 — 1.3 V LDO bypassed for operation up to 792 MHz.

0.925 — 1.3 V LDO bypassed for operation up to 396 MHz.

VDD_SOC_IN

1.225

— 1.3 V 264 MHz < VPU  352 MHz

1.15

— 1.3 V VPU  264 MHz

Standby/DSM Mode VDD_ARM_IN

VDD_ARM23_IN

0.9 — 1.3 V See Table 10, "Stop Mode Current and Power

Consumption," on page 25.

VDD_SOC_IN 0.9 — 1.3 V

VDD_HIGH internal

Regulator

VDD_HIGH_IN

2.8 — 3.3 V Must match the range of voltages that the

rechargeable backup battery supports.

Backup battery supply

range

VDD_SNVS_IN

2.8 — 3.3 V Should be supplied from the same supply as

VDD_HIGH_IN, if the system does not require

keeping real time and other data on OFF state.

USB supply voltages USB_OTG_VBUS 4.4 — 5.25 V —

USB_H1_VBUS 4.4 — 5.25 V —

DDR I/O supply NVCC_DRAM 1.14 1.2 1.3 V LPDDR2

1.425 1.5 1.575 V DDR3

1.283 1.35 1.45 V DDR3_L

Supply for RGMII I/O

power group

NVCC_RGMII 1.15 — 2.625 V • 1.15 V – 1.30 V in HSIC 1.2 V mode

• 1.43 V – 1.58 V in RGMII 1.5 V mode

• 1.70 V – 1.90 V in RGMII 1.8 V mode

• 2.25 V – 2.625 V in RGMII 2.5 V mode

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