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首页"PCIe 3.0规范简介:860页全书最低价"
"PCIe 3.0规范简介:860页全书最低价"
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更新于2023-12-22
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PCIe 3.0是一种高速、高性能的计算机总线标准,它在2010年11月10日发布了其基本规范修订本3.0,该规范总共包含860页的内容。了解的人都知道,在制造和销售PCIe 3.0规范相关产品时,它对整个计算机产业具有非常重要的影响。PCIe 3.0规范在一个时代的发展过程中不断完善自身,它的发布和更新记录可以追溯到2002年7月22日的初始版本发布至今。PCIe 2的版本历史记录包括在此规范版本1.0a中重新整合了C1-C66和E1-E4.17的勘误表;规范版本1.1中合并了批准的勘误表和ECN;规范版本2.0中添加了5.0 GT/s的数据速率,并整合了批准的勘误表和ECN;规范版本2.1中合并了PCI Express基本规范Rev. 2.0(2009年2月27日)的勘误表,并添加了内部错误报告ECN等。
总的来说,了解PCIe 3.0规范的人都知道,这是一个非常重要的标准,并且是整个计算机产业发展的一个重要里程碑。我们了解到,全球各地都有许多人在制造和销售与PCIe 3.0相关的产品,这些产品因为其高速、高性能而备受青睐。PCIe 3.0规范在不断更新和完善自身,以适应不断变化的市场需求和技术发展。此规范的发布和更新均对计算机硬件和软件的开发、设计和应用产生着深远的影响。
在PCIe 3.0规范中,高性能、低成本一直是发展的主题。因此,随着技术的不断进步,PCIe 3.0规范版本的发布和更新,不仅为整个计算机产业提供了更多更好的产品,也使得这些产品在市场上更具竞争力。PCIe 3.0提供了更高的数据传输速率和更低的延迟,使其在大规模并行计算、高性能计算和数据中心应用中表现出色。通过PCIe 3.0规范的不断完善,等到了一种可以更好地满足当今和未来标准的总线。PCIe 3.0规范的发布对整个计算机产业具有深远的影响,使得人类的计算能力再次得到了提升,大大推动了科学技术的发展。
了解PCIe 3.0规范的人都知道,这是一项复杂而又有着重要影响的技术。随着电子产品的不断发展,PCIe3.0规范版本的发布和更新,对整个计算机产业而言,意义重大。PCIe 3.0规范的发布及更新不仅对全球制造商及知名品牌的计算机硬件产业产生了影响,也对计算机软件的开发产生了深远影响。我们知道,PCIe 3.0规范的发展历经了多个阶段,每个阶段都在努力使其更好。我们能看到,全球各地,包括国内的许多企业都在生产和销售与PCIe 3.0相关的产品。这些产品因其高速、高性能而在市场上具有很高的竞争力,也为用户提供了更多更好的选择。
PCIe 3.0规范在发展的过程中,不断优化和改进自身,以满足不断变化的市场需求和技术发展。PCIe 3.0规范的发布和更新,对计算机硬件和软件的生产、设计和应用产生着深远影响。所以,PCIe 3.0规范的影响不仅仅是技术层面上的,它还对整个计算机产业的经济和结构等方面产生了促进作用。
总的来说,PCIe 3.0规范的发布和更新不仅对计算机硬件产业有着深远影响,同时也对各个领域的科技创新和发展产生了直接的促进作用。PCIe 3.0规范的不断完善将进一步推动整个计算机产业的发展,也将为人类的科技创新和发展提供更多更好的机遇。PCIe 3.0规范的发布和更新是整个计算机产业发展和科技进步的重要体现,为我们带来了更多更好的产品和服务,为整个世界的科技发展带来了更广阔的空间。
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
16
FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE......................................... 546
FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES................................................... 564
FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 568
F
IGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT.................................................. 569
F
IGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS...................................................... 571
FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY
MESSAGES ........................................................................................................................... 572
FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 576
F
IGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 576
F
IGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 577
FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER............................................................ 588
FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER................................................................ 595
FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER................................................................ 597
F
IGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER..................................................... 601
F
IGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER.............................................. 602
FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 603
FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE................................................................. 605
FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 605
FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 606
FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 608
FIGURE 7-14: DEVICE CONTROL REGISTER................................................................................. 613
FIGURE 7-15: DEVICE STATUS REGISTER.................................................................................... 620
FIGURE 7-16: LINK CAPABILITIES REGISTER............................................................................... 622
FIGURE 7-17: LINK CONTROL REGISTER..................................................................................... 627
FIGURE 7-18: LINK STATUS REGISTER........................................................................................ 635
FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 638
FIGURE 7-20: SLOT CONTROL REGISTER..................................................................................... 640
FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 644
FIGURE 7-22: ROOT CONTROL REGISTER.................................................................................... 646
FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 647
F
IGURE 7-24: ROOT STATUS REGISTER....................................................................................... 648
FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER........................................................................ 649
F
IGURE 7-26: DEVICE CONTROL 2 REGISTER.............................................................................. 654
F
IGURE 7-27: LINK CAPABILITIES 2 REGISTER............................................................................ 658
FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 660
FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 665
F
IGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT.................................. 668
FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 669
F
IGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE
............................................................................................................................................. 671
FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER........................ 672
F
IGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER........................................................ 673
FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER........................................................... 675
F
IGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER..................................................... 677
F
IGURE 7-37: CORRECTABLE ERROR STATUS REGISTER............................................................. 679
F
IGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 680
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
17
FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 681
FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 683
FIGURE 7-41: ROOT ERROR COMMAND REGISTER...................................................................... 683
F
IGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 685
F
IGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 687
FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 688
FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 689
FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 690
F
IGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 691
F
IGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 692
FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 693
FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 694
FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER.................................................................. 695
F
IGURE 7-52: VC RESOURCE CONTROL REGISTER...................................................................... 697
F
IGURE 7-53: VC RESOURCE STATUS REGISTER......................................................................... 699
FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES........................................... 701
FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES
............................................................................................................................................. 702
FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 703
FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER.................................. 704
FIGURE 7-58: SERIAL NUMBER REGISTER................................................................................... 705
FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 706
FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER............... 707
FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 708
FIGURE 7-62: LINK ENTRY.......................................................................................................... 709
FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 709
FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0.......................................................................... 711
FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1.......................................................................... 712
FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY...................................... 713
FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER...................... 713
F
IGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 714
FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 717
F
IGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 719
F
IGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE................................. 720
FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER.......................................... 721
FIGURE 7-73: POWER BUDGETING DATA REGISTER.................................................................... 722
F
IGURE 7-74: POWER BUDGET CAPABILITY REGISTER ............................................................... 724
FIGURE 7-75: ACS EXTENDED CAPABILITY................................................................................ 725
F
IGURE 7-76: ACS EXTENDED CAPABILITY HEADER ................................................................. 725
FIGURE 7-77: ACS CAPABILITY REGISTER ................................................................................. 726
FIGURE 7-78: ACS CONTROL REGISTER ..................................................................................... 727
F
IGURE 7-79: EGRESS CONTROL VECTOR REGISTER................................................................... 730
FIGURE 7-80: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY......... 731
F
IGURE 7-81: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED
CAPABILITY HEADER........................................................................................................... 731
F
IGURE 7-82: PCI EXPRESS MFVC CAPABILITY STRUCTURE..................................................... 733
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
18
FIGURE 7-83: MFVC EXTENDED CAPABILITY HEADER.............................................................. 733
FIGURE 7-84: PORT VC CAPABILITY REGISTER 1 ....................................................................... 734
FIGURE 7-85: PORT VC CAPABILITY REGISTER 2 ....................................................................... 736
F
IGURE 7-86: PORT VC CONTROL REGISTER .............................................................................. 737
F
IGURE 7-87: PORT VC STATUS REGISTER ................................................................................. 738
FIGURE 7-88: VC RESOURCE CAPABILITY REGISTER.................................................................. 738
FIGURE 7-89: VC RESOURCE CONTROL REGISTER...................................................................... 740
FIGURE 7-90: VC RESOURCE STATUS REGISTER......................................................................... 742
F
IGURE 7-91: PCI EXPRESS VSEC STRUCTURE.......................................................................... 746
F
IGURE 7-92: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER ............................................ 746
FIGURE 7-93: VENDOR-SPECIFIC HEADER .................................................................................. 747
FIGURE 7-94: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE........................................... 748
FIGURE 7-95: RCRB HEADER EXTENDED CAPABILITY HEADER ................................................ 748
F
IGURE 7-96: VENDOR ID AND DEVICE ID ................................................................................. 749
F
IGURE 7-97: RCRB CAPABILITIES ............................................................................................ 750
FIGURE 7-98: RCRB CONTROL................................................................................................... 750
FIGURE 7-99: MULTICAST EXTENDED CAPABILITY STRUCTURE................................................. 751
FIGURE 7-100: MULTICAST EXTENDED CAPABILITY HEADER .................................................... 751
FIGURE 7-101: MULTICAST CAPABILITY REGISTER .................................................................... 752
FIGURE 7-102: MULTICAST CONTROL REGISTER ........................................................................ 753
FIGURE 7-103: MC_BASE_ADDRESS REGISTER ......................................................................... 754
FIGURE 7-104: MC_RECEIVE REGISTER ..................................................................................... 754
FIGURE 7-105: MC_BLOCK_ALL REGISTER............................................................................... 755
FIGURE 7-106: MC_BLOCK_UNTRANSLATED REGISTER............................................................ 756
FIGURE 7-107: MC_OVERLAY_BAR.......................................................................................... 757
FIGURE 7-108: RESIZABLE BAR CAPABILITY............................................................................. 759
FIGURE 7-109: RESIZABLE BAR EXTENDED CAPABILITY HEADER............................................. 759
FIGURE 7-110: RESIZABLE BAR CAPABILITY REGISTER............................................................. 760
FIGURE 7-111: RESIZABLE BAR CONTROL REGISTER ................................................................ 761
FIGURE 7-112: ARI CAPABILITY................................................................................................. 762
F
IGURE 7-113: ARI CAPABILITY HEADER .................................................................................. 763
FIGURE 7-114: ARI CAPABILITY REGISTER ................................................................................ 763
F
IGURE 7-115: ARI CONTROL REGISTER .................................................................................... 764
F
IGURE 7-116: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE .................................. 765
FIGURE 7-117: DPA EXTENDED CAPABILITY HEADER ............................................................... 765
FIGURE 7-118: DPA CAPABILITY REGISTER ............................................................................... 766
F
IGURE 7-119: DPA LATENCY INDICATOR REGISTER................................................................. 767
FIGURE 7-120: DPA STATUS REGISTER ...................................................................................... 767
F
IGURE 7-121: DPA CONTROL REGISTER ................................................................................... 768
FIGURE 7-122: DPA POWER ALLOCATION ARRAY ..................................................................... 768
FIGURE 7-123: LTR EXTENDED CAPABILITY STRUCTURE .......................................................... 769
F
IGURE 7-124: LTR EXTENDED CAPABILITY HEADER................................................................ 769
FIGURE 7-125: MAX SNOOP LATENCY REGISTER ....................................................................... 770
F
IGURE 7-126: MAX NO-SNOOP LATENCY REGISTER................................................................. 770
F
IGURE 7-127: TPH EXTENDED CAPABILITY STRUCTURE .......................................................... 771
F
IGURE 7-128: TPH REQUESTER EXTENDED CAPABILITY HEADER............................................ 772
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
19
FIGURE 7-129: TPH REQUESTER CAPABILITY REGISTER............................................................ 772
FIGURE 7-130: TPH REQUESTER CONTROL REGISTER................................................................ 774
FIGURE 7-131: TPH ST TABLE ................................................................................................... 775
F
IGURE 7-132: SECONDARY PCI EXPRESS EXTENDED CAPABILITY STRUCTURE........................ 776
F
IGURE 7-133: SECONDARY PCI EXPRESS EXTENDED CAPABILITY HEADER.............................. 776
FIGURE 7-134: LINK CONTROL 3 REGISTER ................................................................................ 777
FIGURE 7-135: LANE ERROR STATUS REGISTER ......................................................................... 778
FIGURE 7-136: LANE EQUALIZATION CONTROL REGISTER ......................................................... 778
F
IGURE 7-137: LANE ((MAXIMUM LINK WIDTH – 1):0) EQUALIZATION CONTROL REGISTER .... 779
F
IGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER
COMMUNICATION MODELS.................................................................................................. 784
FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND
CONGESTION........................................................................................................................ 785
F
IGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS
............................................................................................................................................. 790
FIGURE C-1: SCRAMBLING SPECTRUM AT 2.5 GT/S FOR DATA VALUE OF 0 ............................... 810
FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE .................................................................... 819
FIGURE G-1: DEVICE AND PROCESSOR CONNECTED USING A PMUX LINK................................ 827
FIGURE G-2: PMUX LINK .......................................................................................................... 828
FIGURE G-3: PMUX PACKET FLOW THROUGH THE LAYERS ...................................................... 829
FIGURE G-4: PMUX PACKET...................................................................................................... 836
FIGURE G-5: TLP AND PMUX PACKET FRAMING (8B10B ENCODING)....................................... 837
FIGURE G-6: TLP AND PMUX PACKET FRAMING (128B/130B ENCODING)................................ 839
FIGURE G-7: PMUX EXTENDED CAPABILITY ............................................................................. 843
FIGURE G-8: PMUX EXTENDED CAPABILITY HEADER............................................................... 843
FIGURE G-9: PMUX CAPABILITY REGISTER............................................................................... 844
FIGURE G-10: PMUX CONTROL REGISTER................................................................................. 846
FIGURE G-11: PMUX STATUS REGISTER.................................................................................... 847
FIGURE G-12: PMUX PROTOCOL ARRAY ENTRY....................................................................... 850
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
20
Tables
TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 54
T
ABLE 2-2: FMT[2:0] FIELD VALUES ............................................................................................ 59
TABLE 2-3: FMT[2:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 60
T
ABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 61
T
ABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 66
TABLE 2-6: ADDRESS FIELD MAPPING.......................................................................................... 66
TABLE 2-7: HEADER FIELD LOCATIONS FOR NON-ARI ID ROUTING............................................. 68
TABLE 2-8: HEADER FIELD LOCATIONS FOR ARI ID ROUTING..................................................... 68
T
ABLE 2-9: BYTE ENABLES LOCATION AND CORRESPONDENCE................................................... 70
T
ABLE 2-10: ORDERING ATTRIBUTES ........................................................................................... 75
TABLE 2-11: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 76
TABLE 2-12: DEFINITION OF TC FIELD ENCODINGS...................................................................... 76
TABLE 2-13: LENGTH FIELD VALUES FOR ATOMICOP REQUESTS................................................. 77
TABLE 2-14: TPH TLP PREFIX BIT MAPPING ............................................................................... 81
TABLE 2-15: LOCATION OF PH[1:0] IN TLP HEADER.................................................................... 82
TABLE 2-16: PROCESSING HINT ENCODING .................................................................................. 82
TABLE 2-17: LOCATION OF ST[7:0] IN TLP HEADERS .................................................................. 83
TABLE 2-18: MESSAGE ROUTING.................................................................................................. 85
TABLE 2-19: INTX MECHANISM MESSAGES ................................................................................. 86
TABLE 2-20: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 88
TABLE 2-21: POWER MANAGEMENT MESSAGES........................................................................... 90
TABLE 2-22: ERROR SIGNALING MESSAGES ................................................................................. 91
TABLE 2-23: UNLOCK MESSAGE................................................................................................... 92
TABLE 2-24: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 92
TABLE 2-25: VENDOR_DEFINED MESSAGES................................................................................. 93
TABLE 2-26: IGNORED MESSAGES ................................................................................................ 95
TABLE 2-27: LTR MESSAGE ......................................................................................................... 95
TABLE 2-28: OBFF MESSAGE....................................................................................................... 96
T
ABLE 2-29: COMPLETION STATUS FIELD VALUES....................................................................... 98
TABLE 2-30: LOCAL TLP PREFIX TYPES..................................................................................... 101
T
ABLE 2-31: END-END TLP PREFIX TYPES................................................................................. 102
T
ABLE 2-32: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES.......................... 117
TABLE 2-33: CALCULATING LOWER ADDRESS FROM 1
ST
DW BE............................................... 118
TABLE 2-34: ORDERING RULES SUMMARY ................................................................................. 123
T
ABLE 2-35: TC TO VC MAPPING EXAMPLE .............................................................................. 131
TABLE 2-36: FLOW CONTROL CREDIT TYPES ............................................................................. 135
TABLE 2-37: TLP FLOW CONTROL CREDIT CONSUMPTION ........................................................ 135
T
ABLE 2-38: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS .......................................... 136
TABLE 2-39: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION
BY
LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 144
TABLE 2-40: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION
BY
LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 144
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