FPGA FIFO Generator v4.3用户指南：理解和应用详解

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本文档是Xilinx LogiCORE IP的FIFOGenerator v4.3用户指南（UG175），发布日期为2008年3月24日。FIFO（First-In-First-Out，先进先出）是一种在数字系统设计中常见的数据结构，它用于在发送者和接收者之间按顺序传递数据，常用于存储缓冲和数据流控制。FIFOGenerator工具是Xilinx提供的IP核心，用于在Xilinx硬件设备上实现高效且可配置的FIFO功能。该用户指南详细介绍了如何利用FIFOGenerator进行FIFO的设计、配置和集成。内容涵盖了FIFO的基本原理、设计理念、接口规范、参数设置、以及如何利用FIFO来优化系统性能和数据传输。用户将学习到如何设置FIFO的容量、数据宽度、读写策略等关键参数，以及如何处理同步和异步操作，确保数据的正确传输。文档强调了版权问题，指出用户仅能在开发与Xilinx硬件兼容的设计时使用该文档，并且必须获得Xilinx的书面许可才能复制、分发或任何形式地发布文档，包括电子、机械、复印等。此外，Xilinx明确表示不承担因使用文档产生的任何责任，并保留随时更新文档的权利，可能不会提前通知用户。用户还应了解到，文档本身可能存在错误，Xilinx并不承诺提供技术支持或更新。 FIFOGenerator v4.3用户指南提供了深入理解和实施FIFO功能的实用指导，对于从事Xilinx FPGA设计的工程师来说，是不可或缺的技术参考资料。通过阅读和遵循这份文档，设计师能够更好地理解和优化其系统的数据流管理，提高设计效率和系统稳定性。

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UG175 March 24, 2008

Chapter 1: Introduction

Technical Support

For technical support, visit www.support.xilinx.com/. Questions are routed to a team of

engineers with FIFO Generator expertise.

Xilinx will provide technical support for use of this product as described in the LogiCORE

FIFO Generator User Guide. Xilinx cannot guarantee timing, functionality, or support of this

product for designs that do not follow these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the FIFO Generator and the

documentation supplied with the core.

FIFO Generator

For comments or suggestions about the FIFO Generator, please submit a WebCase from

www.s

upport.xilinx.com/. Be sure to include the following information:

• Product name

• Core version number

• Explanation of your comments

Document

For comments or suggestions about this document, please submit a WebCase from

www.s

upport.xilinx.com/. Be sure to include the following information:

• Document title

• Document number

• Page number(s) to which your comments refer

• Explanation of your comments

FIFO Generator v4.3 User Guide www.xilinx.com 17

UG175 March 24, 2008

Chapter 2

Core Overview

This chapter provides an overview of the FIFO Generator configuration options and

interfaces.

Feature Overview

Clock Implementation Operation

The FIFO Generator enables FIFOs to be configured with either independent or common

clock domains for write and read operations. The independent clock configuration of the

FIFO Generator enables the user to implement unique clock domains on the write and read

ports. The FIFO Generator handles the synchronization between clock domains, placing no

requirements on phase and frequency relationships between clocks. A common clock

domain implementation optimizes the core for data buffering within a single clock

domain.

Virtex-5 FPGA Built-in FIFO Support

The FIFO Generator supports the Virtex™-5 FPGA built-in FIFO modules, enabling the

creation of large FIFOs by cascading the built-in FIFOs in both width and depth. The core

expands the capabilities of the built-in FIFOs by utilizing the FPGA fabric to create

optional status flags not implemented in the built-in FIFO macro. The built-in Error

Correction Checking (ECC) feature in the built-in FIFO macro is also available.

Virtex-4 FPGA Built-in FIFO Support

The FIFO Generator supports a single instantiation of the Virtex-4 FPGA built-in FIFO

module. The core also implements a FIFO flag patch (“Solution 1:

Synchronous/Asynchronous Clock Work-Arounds,” defined in the Virtex-4 FPGA User

Guide), based on estimated clock frequencies. This patch is implemented in fabric. See

Appendix A, “Performance Information” for resource utilization estimates.

First-Word Fall-Through

The first-word fall-through (FWFT) feature provides the ability to look ahead to the next

word available from the FIFO without having to issue a read operation. The FIFO

accomplishes this by using output registers which are automatically loaded with data,

when data appears in the FIFO. This causes the first word written to the FIFO to

automatically appear on the data out bus (DOUT). Subsequent user read operations cause

the output data to update with the next word, as long as data is available in the FIFO. The

use of registers on the FIFO DOUT bus improves clock-to-output timing, and the FWFT

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UG175 March 24, 2008

Chapter 2: Core Overview

functionality provides low-latency access to data. This is ideal for applications that require

throttling, based on the contents of the data that are read.

See Table 2-2 for FWFT availability. The use of this feature impacts the behavior of many

other features, such as:

• Read operations (see “First-Word-Fall-Through FIFO Read Operation,” page 52)

•

Programmable empty (see “Non-symmetric Aspect Ratio and First-Word Fall-Through,”

page 68)

• Data counts (see “First-Word Fall-Through Data Count,” page 63 and

“Non-symmetric

Aspect Ratio and First-Word Fall-Through,” page 68

)

Memory Types

The FIFO Generator implements FIFOs built from block RAM, distributed RAM, shift

registers, or the built-in FIFOs for Virtex-4 and Virtex-5 FPGAs. The core combines

memory primitives in an optimal configuration based on the selected width and depth of

the FIFO. Table 2-1 provides best-use recommendations for specific design requirements.

Non-Symmetric Aspect Ratio

The core supports generating FIFOs whose write and read ports have different widths,

enabling automatic width conversion of the data width. Non-symmetric aspect ratios

ranging from 1:8 to 8:1 are supported for the write and read port widths. This feature is

available for FIFOs implemented with block RAM that are configured to have independent

write and read clocks.

Embedded Registers in block RAM and FIFO Macros (Virtex-4 and

Virtex-5 Devices)

In Virtex-4 and Virtex-5 FPGA block RAM and FIFO macros, embedded output registers

are available to increase performance and add a pipeline register to the macros. This fea-

ture can be leveraged to add one additional latency to the FIFO core (DOUT bus and

VALID outputs) or implement the output registers for FWFT FIFOs. See “Embedded Reg-

isters in block RAM and FIFO Macros (Virtex-4 and Virtex-5 FPGAs),” page 69 for more

information.

Table 2-1: Memory Configuration Benefits

Independent

Clocks

Common

Clock

Small

Buffering

Medium-

Large

Buffering

High

Performance

Minimal

Resources

Built-in

FIFO

✔✔ ✔ ✔ ✔

block RAM

✔✔ ✔ ✔ ✔

Shift

✔✔ ✔

Distributed

RAM

✔✔✔ ✔

FIFO Generator v4.3 User Guide www.xilinx.com 19

UG175 March 24, 2008

Core Configuration and Implementation

Error Correction Checking

For the Virtex-5 FPGA architecture, the block RAM and FIFO macros are equipped with

built-in Error Correction Checking (ECC), available for both the common and independent

clock block RAM or built-in based FIFOs.

Core Configuration and Implementation

Table 2-2 provides a summary of the supported memory and clock configurations.

Common Clock: Block RAM, Distributed RAM, Shift Register

This implementation category allows the user to select block RAM, distributed RAM, or

shift register and supports a common clock for write and read data accesses.

The feature set supported for this configuration includes status flags (full, almost full,

empty, and almost empty) and programmable empty and full flags generated with user-

defined thresholds. In addition, optional handshaking and error flags are supported (write

acknowledge, overflow, valid, and underflow), and an optional data count provides the

number of words in the FIFO. In addition, for the block RAM and distributed RAM

implementations, the user has the option to select a synchronous or asynchronous reset for

the core. For Virtex-5 FPGA designs, the block RAM FIFO configuration also supports

ECC.

Common Clock: Virtex-5 or Virtex-4 FPGA Built-in FIFO

This implementation category allows the user to select the built-in FIFO available in the

Virtex-5 or Virtex-4 FPGA architectures and supports a common clock for write and read

data accesses.

Table 2-2: FIFO Configurations

Clock Domain Memory Type

Non-

symmetric

Aspect Ratios

First-Word

Fall-

Through

ECC

Support

Embedded

Support

Common block RAM

✔✔✔

1. Embedded register support is only available for Virtex-4 and Virtex-5 FPGA block RAM-based FIFOs.

Common Distributed

RAM

✔

Common Shift Register

Common Built-in FIFO

2. The built-in FIFO primitive is only available in the Virtex-5 and Virtex-4 architectures.

✔

3. FWFT is only supported for built-in FIFOs in Virtex-5 devices.

✔✔

4. Only available for Virtex-5 FPGA common clock built-in FIFOs.

Independent block RAM

✔

✔✔

✔

Independent Distributed

RAM

✔

Independent Built-in

FIFO

2,5

5. For non-symmetric aspect ratios, use the block RAM implementation (feature not supported in built-in FIFO primitive).

✔

20 www.xilinx.com FIFO Generator v4.3 User Guide

UG175 March 24, 2008

Chapter 2: Core Overview

The feature set supported for this configuration includes status flags (full and empty) and

optional programmable full and empty flags with user-defined thresholds. In addition,

optional handshaking and error flags are available (write acknowledge, overflow, valid,

and underflow). The Virtex-5 FPGA built-in FIFO configuration also supports the built-in

ECC feature.

Independent Clocks: Block RAM and Distributed RAM

This implementation category allows the user to select block RAM or distributed RAM and

supports independent clock domains for write and read data accesses. Operations in the

read domain are synchronous to the read clock and operations in the write domain are

synchronous to the write clock.

The feature set supported for this type of FIFO includes non-symmetric aspect ratios

(different write and read port widths), status flags (full, almost full, empty, and almost

empty), as well as programmable full and empty flags generated with user-defined

thresholds. Optional read data count and write data count indicators provide the number

of words in the FIFO relative to their respective clock domains. In addition, optional

handshaking and error flags are available (write acknowledge, overflow, valid, and

underflow). For Virtex-5 FPGA designs, the block RAM FIFO configuration also supports

ECC.

Independent Clocks: Built-in FIFO for Virtex-5 or Virtex-4 FPGAs

This implementation category allows the user to select the built-in FIFO available in the

Virtex-5 or Virtex-4 FPGA architectures. Operations in the read domain are synchronous to

the read clock and operations in the write domain are synchronous to the write clock.

The feature set supported for this configuration includes status flags (full and empty) and

programmable full and empty flags generated with user-defined thresholds. In addition,

optional handshaking and error flags are available (write acknowledge, overflow, valid,

and underflow). The Virtex-5 FPGA built-in FIFO configuration also supports the built-in

ECC feature.

FIFO Generator Features

Table 2-3 summarizes the FIFO Generator features supported for each clock configuration

and memory type.

Table 2-3: FIFO Configurations Summary

FIFO Feature

Independent Clocks Common Clock

Block RAM

Distributed

RAM

Built-in

FIFO

Block RAM

DistributedR

AM, Shift

Built-in

FIFO

Non-symmetric

Aspect Ratios

✔

Symmetric

Aspect Ratios

✔✔✔✔✔✔

Almost Full

✔✔ ✔✔

Almost Empty

✔✔ ✔✔

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FPGA FIFO Generator v4.3用户指南：理解和应用详解

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sync_fifo.zip，博客对应同步FIFO接口源码（RTL和TB）

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FIFO.rar_FIFO quartus_fifo仿真_quartus 2fifo仿真_quartus fpga fifo_v

fifo摄像头

async_fifo.zip_async fifo_fifo vhdl

FIFO_recalltrm_fifo_verilog_；FIFO_

fifo.zip_fifo_vivado fifo仿真_whichddo

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