"Blackfin®系列嵌入式处理器规格书及外设支持详解"

ADSP

需积分: 9 152 浏览量更新于2024-03-23 收藏 791KB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源推荐

ADSP-BF531/ADSP-BF532/ADSP-BF533

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data-word or

after transferring an entire data buffer or buffers

through DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1,024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

An additional 250 mV of SPORT input hysteresis can be

enabled by setting Bit 15 of the PLL_CTL register. When this bit

is set, all SPORT input pins have the increased hysteresis.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has an

SPI-compatible port that enables the processor to communicate

with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data

pins (master output-slave input, MOSI, and master input-slave

output, MISO) and a clock pin (serial clock, SCK). An SPI chip

select input pin (SPISS

) lets other SPI devices select the proces-

sor, and seven SPI chip select output pins (SPISEL7–1

) let the

processor select other SPI devices. The SPI select pins are recon-

figured general-purpose I/O pins. Using these pins, the SPI port

provides a full-duplex, synchronous serial interface which sup-

ports both master/slave modes and multimaster environments.

The baud rate and clock phase/polarities for the SPI port are

programmable, and it has an integrated DMA controller, con-

figurable to support transmit or receive data streams. The SPI

DMA controller can only service unidirectional accesses at any

given time.

The SPI port clock rate is calculated as:

SCLK

SPI Clock Rate =

------------------------------------

2 × SPI_BAUD

Where the 16-bit SPI_BAUD register contains a value of 2 to

65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pro-

vides a full-duplex universal asynchronous receiver/transmitter

(UART) port, which is fully compatible with PC-standard

UARTs. The UART port provides a simplified UART interface

to other peripherals or hosts, supporting full-duplex, DMA-sup-

ported, asynchronous transfers of serial data. The UART port

includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop

bits, and none, even, or odd parity. The UART port supports

two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The baud rate, serial data format, error code generation and sta-

tus, and interrupts for the UART port are programmable.

The UART programmable features include:

• Supporting bit rates ranging from (f

SCLK

/1,048,576) bits per

second to (f

SCLK

/16) bits per second.

• Supporting data formats from seven bits to 12 bits per

frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

SCLK

UART Clock Rate =

-----------------------------------------------

16 × UART_Divisor

Where the 16-bit UART_Divisor comes from the UART_DLH

significant 8 bits).

In conjunction with the general-purpose timer functions,

autobaud detection is supported.

The capabilities of the UART are further extended with support

for the Infrared Data Association (IrDA) serial infrared physical

layer link specification (SIR) protocol.

GENERAL-PURPOSE I/O PORT F

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has 16

bidirectional, general-purpose I/O pins on Port F (PF15–0).

Each general-purpose I/O pin can be individually controlled by

manipulation of the GPIO control, status and interrupt

registers:

• GPIO direction control register – Specifies the direction of

each individual PFx pin as input or output.

• GPIO control and status registers – The ADSP-BF531/

ADSP-BF532/ADSP-BF533 processor employs a “write one

to modify” mechanism that allows any combination of

individual GPIO pins to be modified in a single instruction,

without affecting the level of any other GPIO pins. Four

control registers are provided. One register is written in

order to set GPIO pin values, one register is written in

order to clear GPIO pin values, one register is written in

order to toggle GPIO pin values, and one register is written

in order to specify GPIO pin values. Reading the GPIO sta-

tus register allows software to interrogate the sense of the

GPIO pin.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual PFx pin to function as

an interrupt to the processor. Similar to the two GPIO con-

trol registers that are used to set and clear individual GPIO

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function. PFx

Rev. E | Page 10 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

pins defined as inputs can be configured to generate hard-

ware interrupts, while output PFx pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual PFx

pins are level- or edge-sensitive and specify—if edge-sensi-

tive—whether just the rising edge or both the rising and

falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects which

edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bi-directional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex bi-

directional transfer of 8- or 10-bit video data. Additionally, on-

chip decode of embedded start-of-line (SOL) and start-of-field

(SOF) preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input mode – Frame syncs and data are inputs into the PPI.

• Frame capture mode – Frame syncs are outputs from the

PPI, but data are inputs.

• Output mode – Frame syncs and data are outputs from the

PPI.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(e.g., for frame capture). The ADSP-BF531/ADSP-BF532/

ADSP-BF533 processors control when to read from the video

source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a

VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

•Active video only mode

• Vertical blanking only mode

• Entire field mode

Active Video Only Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pro-

vides four operating modes, each with a different performance/

power profile. In addition, dynamic power management pro-

vides the control functions to dynamically alter the processor

core supply voltage, further reducing power dissipation. Control

of clocking to each of the processor peripherals also reduces

power consumption. See Table 4 for a summary of the power

settings for each mode.

Rev. E | Page 11 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured L1

memories.

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Table 4. Power Settings

Mode PLL

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Core

Power

Full-On

Active

Sleep

Deep Sleep

Hibernate

Enabled

Enabled/

Disabled

Enabled

Disabled

Yes

Enabled

Disabled

Enabled

Disabled

Off

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity will wake up the

processor. When in the sleep mode, assertion of wakeup will

cause the processor to sense the value of the BYPASS bit in the

PLL control register (PLL_CTL). If BYPASS is disabled, the pro-

cessor will transition to the full-on mode. If BYPASS is enabled,

the processor will transition to the active mode.

When in the sleep mode, system DMA access to L1 memory is

not supported.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but will not be able to

access internal resources or external memory. This powered-

down mode can only be exited by assertion of the reset interrupt

(RESET

) or by an asynchronous interrupt generated by the

RTC. When in deep sleep mode, an RTC asynchronous

interrupt causes the processor to transition to the active mode.

Assertion of RESET

while in deep sleep mode causes the proces-

sor to transition to the full-on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all

the synchronous peripherals (SCLK). The internal voltage regu-

lator for the processor can be shut off by writing b#00 to

the FREQ bits of the VR_CTL register. In addition to disabling

the clocks, this sets the internal power supply voltage (V

DDINT

) to

0 V to provide the lowest static power dissipation. Any critical

information stored internally (memory contents, register con-

tents, etc.) must be written to a nonvolatile storage device prior

to removing power if the processor state is to be preserved.

Since V

DDEXT

is still supplied in this mode, all of the external pins

three-state, unless otherwise specified. This allows other devices

that may be connected to the processor to still have power

applied without drawing unwanted current. The internal supply

regulator can be woken up either by a real-time clock wakeup or

by asserting the RESET

pin.

Power Savings

As shown in Table 5, the ADSP-BF531/ADSP-BF532/

ADSP-BF533 processor supports three different power

domains. The use of multiple power domains maximizes flexi-

bility, while maintaining compliance with industry standards

and conventions. By isolating the internal logic of the processor

into its own power domain, separate from the RTC and other

I/O, the processor can take advantage of dynamic power man-

agement without affecting the RTC or other I/O devices. There

are no sequencing requirements for the various power domains.

Table 5. Power Domains

Power Domain V

Range

All internal logic, except RTC V

DDINT

RTC internal logic and crystal I/O V

DDRTC

All other I/O V

DDEXT

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive, in

that if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

The dynamic power management feature of the ADSP-BF531/

ADSP-BF532/ADSP-BF533 processor allows both the proces-

sor’s input voltage (V

DDINT

) and clock frequency (f

CCLK

) to be

dynamically controlled.

The savings in power dissipation can be modeled using the

power savings factor and % power savings calculations.

Rev. E | Page 12 of 60 | July 2007

剩余59页未读，继续阅读

liuy5134

粉丝: 0
资源: 5

会员权益专享

"Blackfin®系列嵌入式处理器规格书及外设支持详解"

ADSP-BF531、ADSP-BF532、ADSP-BF533.pdf

ADSP-BF531-BF532-BF533.doc

ADSP-BF531SBBC400.pdf

ADSP-BF531这么烧录

ADSP-BF532

ADSP-2171-EZ-ICE-P

adsp-21489中文数据手册

adsp-21363KSWZ-1AA

反汇编ADSP-21479

反汇编ADSP-21489详细步骤

adsp-21364

adsp-sc582数据手册

ADSP-21569

adsp21489 中文资料

adi adsp21477

推荐入门DSP开发板

ADSP CM408开发板软件

bf526 dsp烧写ldr程序步骤

封装一定是QFN48，4 5 6 7脚可以做SPI外接存储，22脚是BCR，38脚是FSKVDD，47脚是RFIN，12脚和13脚是晶振输入 应用在数据传输 最相近的IC是什么

DSP编写汇编和C混合的DSP程序连接命令程序

会员权益专享

最新资源

封装一定是QFN48，4 5 6 7脚可以做SPI外接存储，22脚是BCR，38脚是FSKVDD，47脚是RFIN，12脚和13脚是晶振输入应用在数据传输最相近的IC是什么