VHDL实战教程（第4版）：设计方法与实例

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"《VHDL编程实战第四版》是Douglas L. Perry所著的一本经典教材，专为学习VHDL语言及其设计方法论而设计。作为第四版，该书不仅全面覆盖VHDL语言特性，还深入讲解了设计流程，包括从设计构思到实际应用的各个环节。读者将跟随作者的脚步，学习如何创建VHDL设计、进行模拟、综合、布线、以及利用VITAL仿真技术验证最终结果。本书新增了一项名为At-Speed调试的技术，这项技术能极大地提高设计验证的效率。在设计示例部分，作者对先前的关注点进行了更新，更加注重设计方法学，以帮助读者理解并掌握如何在实际项目中应用VHDL。这本书特别强调实践与理论的结合，通过实例让学习者能够熟练掌握VHDL编程技巧。版权方面，所有内容受到1976年美国版权法保护，未经出版商事先书面许可，禁止任何形式的复制或分发。值得注意的是，书中提到的所有商标均为各自所有者的财产，书中采用编辑性方式引用，尊重知识产权。对于需要批量购买或用于培训项目的读者，McGraw-Hill公司提供了优惠折扣信息，如有兴趣，可通过乔治·霍尔联系获取更多详情。《VHDL编程实战第四版》是一本既实用又系统的学习指南，无论是初学者还是经验丰富的工程师，都能从中收获丰富的知识和技能，提升在硬件描述语言（VHDL）领域的专业能力。"

PREFACE

This is the fourth version of the book and this version now not only provides

VHDL language coverage but design methodology information as well. This

version will guide the reader through the process of creating a VHDL

design, simulating the design, synthesizing the design, placing and routing

the design, using VITAL simulation to verify the final result, and a new

technique called At-Speed debugging that provides extremely fast design

verification. The design example in this version has been updated to reflect

the new focus on the design methodology.

This book was written to help hardware design engineers learn how to

write good VHDL design descriptions. The goal is to provide enough VHDL

and design methodology information to enable a designer to quickly write

good VHDL designs and be able to verify the results. It will also attempt

to bring the designer with little or no knowledge of VHDL, to the level of

writing complex VHDL descriptions. It is not intended to show every pos-

sible construct of VHDL in every possible use, but rather to show the de-

signer how to write concise, efficient, and correct VHDL descriptions of

hardware designs.

This book is organized into three logical sections. The first section of the

book will introduce the VHDL language, the second section walks through

a VHDL based design process including simulation, synthesis, place and

route, and VITAL simulation; and the third section walks through a design

example of a small CPU design from VHDL capture to final gate-level

implementation, and At-Speed debugging. At the back of the book are

included a number of appendices that contain useful information about the

language and examples used throughout the book.

In the first section VHDL features are introduced one or more at a time.

As each feature is introduced, one or more real examples are given to show

how the feature would be used. The first section consists of Chapters 1

through 8, and each chapter introduces a basic description capability of

VHDL. Chapter 1 discusses how VHDL design relates to schematic based

design, and introduces the basic terms of the language. Chapter 2 describes

some of the basic concepts of VHDL, including the different delay mecha-

nisms available, how to use instance specific data, and defines VHDL dri-

vers. Chapter 2 discusses concurrent statements while Chapter 3 introduces

the reader to VHDL sequential statements. Chapter 4 talks about the wide

Preface

xvi

range of types available for use in VHDL. Examples are given for each of

the types showing how they would be used in a real example. In Chapter

5 the concepts of subprograms and packages are introduced. The different

uses for functions are given, as well as the features available in VHDL

packages.

Chapter 6 introduces the five kinds of VHDL attributes. Each attribute

kind has examples describing how to use the specific attribute to the

designer’s best advantage. Examples are given which describe the pur-

pose of each of the attributes.

Chapters 7 and 8 will introduce some of the more advanced VHDL

features to the reader. Chapter 7 discusses how VHDL configurations

can be used to construct and manage complex VHDL designs. Each of

the different configuration styles are discussed along with examples

showing usage. Chapter 8 introduces more of the VHDL advanced top-

ics with discussions of overloading, user defined attributes, generate

statements, and TextIO.

The second section of the book consists of Chapters 9 through 11. Chap-

ters 9 and 10 discuss the synthesis process and how to write synthesiz-

able designs. These two chapters describe the basics of the synthesis

process including how to write synthesizeable VHDL, what is a technol-

ogy library, what does the synthesis process look like, what are con-

straints and attributes, and what does the the optimization process look

like. Chapter 11 discusses the complete high level design flow from VHDL

capture through VITAL simulation.

The third section of the book walks through a description of a small

CPU design from the VHDL capture through simulation, synthesis, place

and route, and VITAL simulation. Chapter 12 describes the top level of

the CPU design from a functional point of view. In Chapter 13 the RTL

description of the CPU is presented and discussed from a synthesis point

of view. Chapter 14 begins with a discussion of VHDL testbenches and

how they are used to verify functionality. Chapter 14 finishes the discus-

sion by describing the simulation of the CPU design. In Chapter 15 the

verified design is synthesized to a target technology. Chapter 16 takes

the synthesized design and places and routes the design to a target

device. Chapter 17 begins with a discussion of VITAL and ends with the

VITAL simulation of the placed and routed CPU design. Chapter 18 is a

new chapter that discusses the new technique of At-Speed debugging.

This chapter provides the reader with an in-depth look at how a hardware

implementation of the CPU design can help speed verification.

Finally there are three appendices at the end of the book to provide ref-

erence information. Appendix A is a listing of the IEEE 1164 STD_LOGIC

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