低功耗TLV320AIC3106：立体声音频编解码器详解

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TI-TLV320AIC3106是一款专为便携式音频和电话应用设计的高性能低功耗立体声音频编解码器。这款芯片的核心特性包括： 1. **立体声音频DAC**：它具备出色的信噪比，可达102dB，支持16、20、24、32位数据，工作频率范围从8kHz到96kHz，提供了丰富的音频处理能力，如3D、低音增强、高音调整、均衡器和去加重等。它还支持多种节能模式和灵活的性能设置，以适应不同的功耗需求。 2. **立体声音频ADC**：具有92dBA的信噪比，同样支持8kHz至96kHz的采样率，录音期间还具备数字信号处理和噪声滤除功能，确保录音质量。 3. **音频输入和输出接口**：拥有十个可编程的音频输入引脚，支持单端或全差分配置，并且可以用于浮点输入，配备三态功能。输出方面，有七个驱动器，包括立体声全差动或单端耳机驱动器，以及全差动立体声线路输出和单声道输出，能够满足各种输出需求。 4. **低功耗设计**：该芯片在3.3V模拟电源下播放立体声时，功耗仅为15mW，非常适合电池供电的便携设备。此外，还提供了超低功耗模式，带有无源模拟旁路，以进一步节省能源。 5. **电源管理**：支持广泛的模块化电源控制，包括模拟电源（2.7V至3.6V）、数字内核电源（1.65V至1.95V）和数字I/O电源（1.1V至3.6V）。不同的电源选项满足不同组件的需求。 6. **接口灵活性**：控制总线支持SPI或I2C，音频数据总线支持I2S、左平衡和右平衡、DSP和TDM模式，便于与蓝牙模块和其他设备通信。同时，兼容数字和模拟麦克风，支持并发操作。 7. **功能齐全**：录音功能集成自动增益控制（AGC）和可编程麦克风偏置电平，以及用于灵活时钟生成的可编程PLL。此外，还提供全面的寄存器级电源控制，便于系统开发者进行配置。 8. **封装形式**：有两种封装规格，分别为5.00mm×5.00mm的80引脚VFBGA和7.00mm×7.00mm的48引脚VQFN，满足不同尺寸和空间限制的应用。这款编解码器适用于各种便携式设备，如数码相机和智能手机，因其高效的能效和全面的功能集而备受青睐，尤其适合那些对音质和电池寿命有高要求的移动音频和电话应用。

10.2 Functional Block Diagram

AudioSerialBusInterface

MIC3L /LINE3L

PGA

0/+59.5dB

0.5dBsteps

ADC

HPRCOM

HPLCOM

HPLOUT

VCM

DAC

Volume

Control

Effects

DIN

DOUT

BCLK

WCLK

DINL

DINR

DOUTL

DOUTR

AGC

SW-D2

SW-D1

SPI/I2CSerialControlBus

SELECT

CSEL/I2C_ADR0

SCLK/I2C_ADR1

MOSI/GPIO

MISO/GPIO

Bias/

Reference

MICBIAS

SCL/GPIO

SDA/GPIO

RESET

MICDET

VoltageSupplies

DVDD

DRVDD

DRVSS

DVSS

IOVDD

AVDD_ADC

AVSS_ADC

AVDD_DAC

AVSS_DAC

AudioClock

Generation

MCLK

GPIO_1

GPIO_2

HPROUT

MIC3R/LINE3R

ADC

PGA

0/+59.5dB

0.5dBsteps

DACR

Volume

Control

Effects

AGC

SW-D3

SW-D4

MONO_LOP

MONO_LOM

LINE1RP

LINE2RM

LINE2RP

LINE1RM

SW-R0

SW-R3

SW-R1

SW-R2

SW-R4

SW-R5

RIGHT_LOP

RIGHT_LOM

LINE1LP

LINE2LM

LINE2LP

LINE1LM

SW-L0

SW-L3

SW-L1

SW-L2

SW-L4

SW-L5

LEFT_LOP

LEFT_LOM

MIC2RM/LINE2RM

MIC2RP /LINE2RP

LINE2RP

LINE2RM

MIC1RM/LINE1RM

MIC1RP /LINE1RP

LINE1RP

LINE1RM

MIC2LM/LINE2LM

MIC2LP /LINE2LP

LINE2LP

LINE2LM

MIC1LM/LINE1LM

MIC1LP /LINE1LP

LINE1LP

LINE1LM

10.3 Feature Description

10.3.1 Hardware Reset

The TLV320AIC3106 requires a hardware reset after power-up for proper operation. After all power supplies are

at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not

performed, the TLV320AIC3106 may not respond properly to register reads/writes.

10.3.2 Digital Audio Data Serial Interface

Audio data is transferred between the host processor and the TLV320AIC3106 via the digital audio data serial

interface, or audio bus. The audio bus on this device is very flexible, including left or right justified data options,

support for I

S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,

very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple

devices within a system directly.

The data serial interface uses two sets of pins for communication between external devices, with the particular

pin used controlled through register programming. This configuration is illustrated in 图 10-1.

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AudioSerialDataBus

DOUT

GPIO1 GPIO2 MFP3

WCLK BCLK DIN

图 10-1. Alternate Audio Bus Mulitplexing Function

In cases where MFP3 is needed for a secondary device digital input, the TLV320AIC3106 must be used in I

mode (when in SPI mode, MFP3 is used as the SPI bus MOSI pin and thus cannot be used here as an alternate

digital input source).

This mux capability allows the TLV320AIC3106 to communicate with two separate devices with independent

S/PCM buses. An example of such an application is a cellphone containing a Bluetooth transceiver with

PCM/I

S interface, as shown in 图 10-2. The applications processor can be connected to the WCLK, BCLK, DIN,

DOUT pins on the TLV320AIC3106, while a Bluetooth device with PCM interface can be connected to the

GPIO1, GPIO2, MFP3, and DOUT pins on the TLV320AIC3106. By programming the registers via I

C control,

the applications processor can determine which device is communicating with the TLV320AIC3106. This is

attractive in cases where the TLV320AIC3106 can be configured to communicate data with the Bluetooth device,

then the applications processor can be put into a low power sleep mode, while voice/audio transmission still

occurs between the Bluetooth device and the TLV320AIC3106.

PossibleProcessor Types:

ApplicationProcessor,MultimediaProcessor,

Compressed AudioDecoder,WirelessModem,

BluetoothModule, Additional Audio/VoiceCodec

Processor

GPIO2

WCLK

BCLK

DIN

DOUT

MFP3

GPIO1

AIC3106

图 10-2. TLV320AIC3106 Connected to Multiple Audio Devices

The audio bus of the TLV320AIC3106 can be configured for left or right justified, I

S, DSP, or TDM modes of

operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.

These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word

clock (WCLK or GPIO1) and bit clock (BCLK or GPIO2) can be independently configured in either Master or

Slave mode, for flexible connectivity to a wide variety of processors

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The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either

a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC

and DAC sampling frequencies.

The bit clock (BCLK or GPIO2) is used to clock in and out the digital audio data across the serial bus. When in

Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock

mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are

generated, so in general the number of bit clocks per frame will be two times the data width. For example, if data

width is chosen as 16 bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode

will be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be

used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × f

or 64 × f

In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame will not all be

of equal period, due to the device not having a clean 40 × f

or 48 × f

clock signal readily available. The

average frequency of the bit clock signal is still accurate in these cases (being 40 × f

or 48 × f

), but the

resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.

The TLV320AIC3106 further includes programmability to 3-state the DOUT line during all bit clocks when valid

data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the

audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to

use a single audio serial data bus.

When the audio serial data bus is powered down while configured in master mode, the pins associated with the

interface will be put into a 3-state output condition.

10.3.2.1 Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling

edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding

the rising edge of the word clock.

BCLK

WCLK

SDIN/

SDOUT

1 00 1 0

1/fs

LSBMSB

LeftChannel RightChannel

2 2

n−1

n−3

n−2

n−1

n−3

n−2

图 10-3. Right-Justified Serial Bus Mode Operation

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