CS8900A中文手册：单片以太网控制器详解

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"这是一个关于CS8900A网卡的手册，其中包含了详细的芯片工作模式、寄存器设置以及各种特性介绍。这份手册是Cirrus Logic公司在2007年发布的，旨在提供全面的技术支持和软件驱动程序，适用于工业温度范围的操作环境。" CS8900A是一款单芯片的IEEE 802.3以太网控制器，它具有直接与ISA总线接口的设计，最大电流消耗为55mA（在5V供电下）。该芯片能在3V或5V电压下工作，满足不同系统的需求，并且能够在极端的工业温度范围内稳定运行。手册中详细阐述了其硬件设计和电气特性，这对于理解和调试基于CS8900A的网络设备至关重要。该控制器具备全双工操作能力，内置的RAM缓冲区用于存储发送和接收的数据帧，提高了数据处理效率。CS8900A还支持自动极性检测和校正功能，确保了10BASE-T端口的物理连接可靠性。同时，它也配备了AUI端口，可以兼容10BASE2、10BASE5和10BASE-F等不同类型的以太网标准。在传输特性方面，CS8900A具备自动重传碰撞、自动填充和CRC生成等功能，以应对网络中的冲突和错误。而在接收端，其采用Stream Transfer技术降低CPU负载，能够自动在DMA和片上内存之间切换，提前中断处理以优化性能，并能自动过滤掉错误的包，保证了数据的完整性和准确性。此外，CS8900A支持EEPROM，实现了无跳线配置，简化了硬件安装过程。对于无硬盘系统，它还支持BootPROM，使得无盘系统的启动变得可能。该芯片还集成了边界扫描和环回测试功能，便于故障诊断和调试。LED驱动器的集成则方便了状态指示灯的控制，使用户可以直观了解设备的工作状态。这份有批注的CS8900A产品数据表提供了丰富的信息，不仅涵盖了硬件设计，还包括了软件驱动、配置选项以及故障排除等多个层面，是工程师进行产品开发、维护和故障诊断的重要参考资料。

16 DS271F4

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

General Pins

XTAL[1:2] - Crystal, Input/Output PINS 97 and 98.

A 20 MHz crystal should be connected across these pins. If a crystal is not used, a 20

MHz signal should be connected to XTAL1 and XTAL2 should be left open. (See

Section 7.3 on page 112 and Section 7.7 on page 122.)

SLEEP - Hardware Sleep, Input Internal Weak Pullup PIN 77.

Active-low input used to enable the two hardware sleep modes: Hardware Suspend

and Hardware Standby. (See Section 3.7 on page 27.)

LINKLED or HC0 - Link Good LED or Host Controlled Output 0, Open Drain Output PIN

99.

When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low

output is low when the CS8900A detects the presence of valid link pulses. When the

HC0E bit is set, the host may drive this pin low by setting the HCBO in the Self

Control register.

BSTATUS or HC1 - Bus Status or Host Controlled Output 1, Open Drain Output PIN 78.

When the HC1E bit of the Self Control register (Register 15) is clear, this active-low

output is low when receive activity causes an ISA bus access. When the HC1E bit is

set, the host may drive this pin low by setting the HCB1 in the Self Control register.

LANLED - LAN Activity LED, Open Drain Output PIN 100.

During normal operation, this active-low output goes low for 6 ms whenever there is a

receive packet, a transmit packet, or a collision. During Hardware Standby mode, this

output is driven low when the receiver detects network activity.

TEST - Test Enable, Input Internal Weak Pullup PIN 76.

Active-low input used to put the CS8900A in Boundary Scan Test mode. For normal

operation, this pin should be high.

RES - Reference Resistor, Input PIN 93.

This input should be connected to a 4.99KΩ ± 1% resistor needed for biasing of

internal analog circuits.

DVDD[1:4] - Digital Power, Power PINS 9, 22, 56, and 69.

Provides 5 V ± 5% power to the digital circuits of the CS8900A.

DVSS[1:4} and DVSS1A, DVSS3A - Digital Ground, Ground PINS 8, 10, 23, 55, 57, and

70.

Provides ground reference (0 V) to the digital circuits of the CS8900A.

AVDD[1:3] - Analog Power, Power PINS 90, 85, and 95.

Provides 5 V ± 5% power to the analog circuits of the CS8900A.

AVSS[0:4] - Analog Ground, Ground PINS 1, 89, 86, 94, 96.

Provide ground reference (0 V) to the analog circuits of the CS8900A.

DS271F4 17

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview

During normal operation, the CS8900A per-

forms two basic functions: Ethernet packet

transmission and reception. Before transmis-

sion or reception is possible, the CS8900A

must be configured.

3.1.1 Configuration

The CS8900A must be configured for packet

transmission and reception at power-up or re-

set. Various parameters must be written into

its internal Configuration and Control registers

such as Memory Base Address; Ethernet

Physical Address; what frame types to re-

ceive; and which media interface to use. Con-

figuration data can either be written to the

CS8900A by the host (across the ISA bus), or

loaded automatically from an external EE-

PROM. Operation can begin after configura-

tion is complete.

Section 3.3 on page 19 and Section 3.4 on

page 21 describe the configuration process in

detail. Section 4.4 on page 49 provides a de-

tailed description of the bits in the Configura-

tion and Control Registers.

3.1.2 Packet Transmission

Packet transmission occurs in two phases. In

the first phase, the host moves the Ethernet

frame into the CS8900A’s buffer memory. The

first phase begins with the host issuing a

Transmit Command. This informs the

CS8900A that a frame is to be transmitted and

tells the chip when to start transmission (i.e. af-

ter 5, 381, 1021 or all bytes have been trans-

ferred) and how the frame should be sent (i.e.

with or without CRC, with or without pad bits,

etc.). The Host follows the Transmit Command

with the Transmit Length, indicating how much

buffer space is required. When buffer space is

available, the host writes the Ethernet frame

into the CS8900A’s internal memory, either as

a Memory or I/O space operation.

In the second phase of transmission, the

CS8900A converts the frame into an Ethernet

packet then transmits it onto the network. The

second phase begins with the CS8900A trans-

mitting the preamble and Start-of-Frame de-

limiter as soon as the proper number of bytes

has been transferred into its transmit buffer (5,

381, 1021 bytes or full frame, depending on

configuration). The preamble and Start-of-

Frame delimiter are followed by the Destina-

tion Address, Source Address, Length field

and LLC data (all supplied by the host). If the

frame is less than 64 bytes, including CRC, the

CS8900A adds pad bits if configured to do so.

Finally, the CS8900A appends the proper 32-

bit CRC value.

The Section 5.6 on page 99 provides a de-

tailed description of packet transmission.

3.1.3 Packet Reception

Like packet transmission, packet reception oc-

curs in two phases. In the first phase, the

CS8900A receives an Ethernet packet and

stores it in on-chip memory. The first phase of

packet reception begins with the receive frame

passing through the analog front end and

Manchester decoder where Manchester data

is converted to NRZ data. Next, the preamble

and Start-of-Frame delimiter are stripped off

and the receive frame is sent through the ad-

dress filter. If the frame’s Destination Address

matches the criteria programmed into the ad-

dress filter, the packet is stored in the

CS8900A’s internal memory. The CS8900A

then checks the CRC, and depending on the

configuration, informs the processor that a

frame has been received.

In the second phase, the host transfers the re-

ceive frame across the ISA bus and into host

memory. Receive frames can be transferred

18 DS271F4

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

as Memory space operations, I/O space oper-

ations, or as DMA operations using host DMA.

Also, the CS8900A provides the capability to

switch between Memory or I/O operation and

DMA operation by using Auto-Switch DMA

and StreamTransfer.

The Section 5.2 on page 78 through

Section 5.5 on page 96 provide a detailed de-

scription of packet reception.

3.2 ISA Bus Interface

The CS8900A provides a direct interface to

ISA buses running at clock rates from 8 to 11

MHz. Its on-chip bus drivers are capable of de-

livering 24 mA of drive current, allowing the

CS8900A to drive the ISA bus directly, without

added external “glue logic”.

The CS8900A is optimized for 16-bit data

transfers, operating in either Memory space,

I/O space, or as a DMA slave.

Note that ISA-bus operation below 8 MHz

should use the CS8900A’s Receive DMA

mode to minimize missed frames. See

Section 5.3 on page 90 for a description of Re-

ceive DMA operation.

3.2.1 Memory Mode Operation

When configured for Memory Mode operation,

the CS8900A’s internal registers and frame

buffers are mapped into a contiguous 4-Kbyte

block of host memory, providing the host with

direct access to the CS8900A’s internal regis-

ters and frame buffers. The host initiates Read

operations by driving the MEMR

pin low and

Write operations by driving the MEMW pin low.

For additional information about Memory

Mode, see Section 4.9 on page 73.

3.2.2 I/O Mode Operation

When configured for I/O Mode operation, the

CS8900A is accessed through eight, 16-bit I/O

ports that are mapped into sixteen contiguous

I/O locations in the host system’s I/O space.

I/O Mode is the default configuration for the

CS8900A and is always enabled.

For an I/O Read or Write operation, the AEN

pin must be low, and the 16-bit I/O address on

the ISA System Address bus (SA0 - SA15)

must match the address space of the

CS8900A. For a Read, IOR

must be low, and

for a Write, IOW must be low.

For additional information about I/O Mode, see

Section 4.10 on page 75.

3.2.3 Interrupt Request Signals

The CS8900A has four interrupt request out-

put pins that can be connected directly to any

four of the ISA bus Interrupt Request signals.

Only one interrupt output is used at a time. It is

selected during initialization by writing the in-

terrupt number (0 to 3) into PacketPage Mem-

ory base + 0022h. Unused interrupt request

pins are placed in a high-impedance state.

The selected interrupt request pin goes high

when an enabled interrupt is triggered. The pin

goes low after the Interrupt Status Queue

(ISQ) is read as all 0’s (see Section 5.1 on

page 78 for a description of the ISQ).

Table 2 presents one possible way of connect-

ing the interrupt request pins to the ISA bus

that utilizes commonly available interrupts and

facilitates board layout.

3.2.4 DMA Signals

The CS8900A interfaces directly to the host

DMA controller to provide DMA transfers of re-

ceive frames from CS8900A memory to host

CS8900A Interrupt

Request Pin

ISA Bus

Interrupt

PacketPage

base + 0022h

INTRQ3 (Pin 35) IRQ5 0003h

INTRQ0 (Pin 32) IRQ10 0000h

INTRQ1 (Pin 31) IRQ11 0001h

INTRQ2 (Pin 30) IRQ12 0002h

Table 2. Interrupt Assignments

DS271F4 19

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

memory. The CS8900A has three pairs of

DMA pins that can be connected directly to the

three 16-bit DMA channels of the ISA bus.

Only one DMA channel is used at a time. It is

selected during initialization by writing the

number of the desired channel (0, 1 or 2) into

PacketPage Memory base + 0024h. Unused

DMA pins are placed in a high-impedance

state. The selected DMA request pin goes

high when the CS8900A has received frames

to transfer to the host memory via DMA. If the

DMABurst bit (register 17, BusCTL, Bit B) is

clear, the pin goes low after the DMA operation

is complete. If the DMABurst bit is set, the pin

goes low 32 µs after the start of a DMA trans-

fer.

The DMA pin pairs are arranged on the

CS8900A to facilitate board layout. Crystal

recommends the configuration in Table 3

when connecting these pins to the ISA bus.

For a description of DMA mode, see

Section 5.3 on page 90.

3.3 Reset and Initialization

3.3.1 Reset

Seven different conditions cause the

CS8900A to reset its internal registers and cir-

cuits.

3.3.1.1 External Reset, or ISA Reset

There is a chip-wide reset whenever the RE-

SET pin is high for at least 400 ns. During a

chip-wide reset, all circuitry and registers in

the CS8900A are reset.

3.3.1.2 Power-Up Reset

When power is applied, the CS8900A main-

tains reset until the voltage at the supply pins

reaches approximately 2.5 V. The CS8900A

comes out of reset once Vcc is greater than

approximately 2.5 V and the crystal oscillator

has stabilized.

3.3.1.3 Power-Down Reset

If the supply voltage drops below approximate-

ly 2.5 V, there is a chip-wide reset. The

CS8900A comes out of reset once the power

supply returns to a level greater than approxi-

mately 2.5 V and the crystal oscillator has sta-

bilized.

3.3.1.4 EEPROM Reset

There is a chip-wide reset if an EEPROM

checksum error is detected (see Section 3.4

on page 21).

3.3.1.5 Software Initiated Reset

There is a chip-wide reset whenever the RE-

SET bit (Register 15, SelfCTL, Bit 6) is set.

3.3.1.6 Hardware (HW) Standby or Suspend

The CS8900A goes though a chip-wide reset

whenever it enters or exits either HW Standby

mode or HW Suspend mode (see Section 3.7

on page 27 for more information about HW

Standby and Suspend).

3.3.1.7 Software (SW) Suspend

Whenever the CS8900A enters SW Suspend

mode, all registers and circuits are reset ex-

cept for the ISA I/O Base Address register (lo-

cated at PacketPage base + 0020h) and the

SelfCTL register (Register 15). Upon exit,

there is a chip-wide reset (see Section 3.7 on

page 27 for more information about SW Sus-

pend).

CS8900A DMA

Signal (Pin #)

ISA DMA

Signal

PacketPage

base + 0024h

DMARQ0 (Pin 15) DRQ5 0000h

DMACK0

(Pin 16) DACK5

DMARQ1 (Pin 13) DRQ6 0001h

DMACK1

(Pin 14) DACK6

DMARQ2 (Pin 11) DRQ7 0002h

DMACK2

(Pin 12) DACK7

Table 3. DMA Assignments

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