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首页BCM5328X:集成高速交换系统芯片数据手册
BCM5328X:集成高速交换系统芯片数据手册
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更新于2024-07-18
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BCM5328x是一款由博通公司(Broadcom)设计的第十代RoboSwitch™系列交换机芯片,基于先前成功的BCM53242和BCM53262产品。这款65纳米CMOS集成器件集成了高速交换系统的所有关键功能,包括包缓冲器、物理层接口、媒体访问控制器(MAC)、地址管理和一个无阻塞的交换架构。它严格按照IEEE 802.3和IEEE 802.3x标准设计,支持MAC控制PAUSE帧、自动协商以及与所有行业标准的以太网和快速以太网设备兼容。
该芯片的核心特点是具有8个、16个或24个全双工10BASE-T/100BASE-TX快速以太网收发器,每个都能在Cat3、Cat4或Cat5无屏蔽双绞线(UTP)电缆上执行10BASE-T以太网的物理层功能,以及在Cat5 UTP电缆上执行100BASE-TX快速以太网功能。它提供了两种接口选项:两个GMII/RGMII接口,或者四个SGMII/SerDes接口,这使得它在灵活性和可扩展性方面具备优势,可以根据不同的应用需求进行配置。
此外,BCM5328x交换机设计目标是提供高效能、低延迟的数据传输,适合于各种商业网络环境,如企业局域网(LAN)、数据中心和电信级基础设施。它的设计考虑了电源效率,有助于降低总体拥有成本,并且能够处理大量的并发连接,确保网络通信的稳定性和可靠性。
BCM5328x是一款高度集成的以太网交换芯片,凭借其强大的功能集、广泛的接口选项和严格的行业标准兼容性,为现代网络基础设施提供了关键的构建块,推动了网络技术的演进和发展。对于网络工程师和系统设计师来说,理解并利用这款芯片的特性,能够优化网络性能和部署效率。
7/30/2009 PJ87F
BCM5328X Data Sheet
07/14/09
Broadcom Corporation
Page xvi Document 5328X-DS200-R
Page 03H: Management Mode Registers...............................................................................................220
GLOBAL MANAGEMENT CONFIGURATION Register (PAGE 03H/ADDR 00H)...............220
AGING TIME CONTROL Register (PAGE 03H/ADDR 04H) ...............................................221
MIRROR CONTROL Register (PAGE 03H/ADDR 10H) ......................................................221
MIRROR CAPTURE PORT Register (PAGE 03H/ADDR 18H) ...........................................222
INGRESS MIRROR PORT Register (PAGE 03H/ADDR 20H) ............................................223
EGRESS MIRROR PORT Register (PAGE 03H/ADDR 28H).............................................223
SPECIAL MANAGEMENT CONTROL Register (PAGE 03H/ADDR 40H)...........................224
INGRESS RMON CONTROL Register (PAGE 03H/ADDR 60H) .......................................224
INGRESS RMON PORT Register (PAGE 03H/ADDR 68H) ................................................224
EGRESS RMON CONTROL Register (PAGE 03H/ADDR 70H)..........................................225
FULL CHIP RESET CONTROL Register (PAGE 03H/ADDR 7CH).....................................225
TABLE MEMORY RESET CONTROL Register (PAGE 03H/ADDR 7EH)...........................225
Page 04H: ARL Control Registers...........................................................................................................229
GLOBAL ARL CONFIGURATION Register (PAGE 04H/ADDR 00H)..................................229
STP BYPASS CONTROL Register (PAGE 04H/ADDR 02H) .............................................229
MSTP CONTROL Register (PAGE 04H/ADDR 0AH) .........................................................230
FAST AGING CONTROL Register (PAGE 04H/ADDR 0BH) .............................................230
AGE OUT CONTROL Register (PAGE 04H/ADDR 0CH)...................................................231
L2 USER ADDRESS 1 Register (PAGE 04H/ADDR 10H)...................................................232
L2 USER VECTOR 1 Register (PAGE 04H/ADDR 18H) .....................................................232
L2 USER ADDRESS 2 Register (PAGE 04H/ADDR 20H)..................................................232
L2 USER VECTOR 2 Register (PAGE 04H/ADDR 28H) .....................................................233
PAUSE FRAME SOURCE ADDRESS Register (PAGE 04H/ADDR 80H)...........................233
Page 07H: Memory Search Registers .....................................................................................................234
MEMORY/TABLE INDEX Register (PAGE 07H/ADDR 00H)...............................................234
MEMORY CONTROL Register (PAGE 07H/ADDR 08H) ....................................................235
MEMORY ADDRESS/OFFSET Register (PAGE 07H/ADDR 10H) .....................................236
MEMORY DATA 0 Register (PAGE 07H/ADDR 20H) .........................................................236
MEMORY DATA 1 Register (PAGE 07H/ADDR 28H) .........................................................237
MEMORY KEY 2 Register (PAGE 07H/ADDR 90H)............................................................237
Page 08H: Memory Access Registers.....................................................................................................238
MEMORY/TABLE INDEX Register (PAGE 08H/ADDR 00H)...............................................239
MEMORY CONTROL Register (PAGE 08H/ADDR 08H) ....................................................239
GROUP CONTROL Register (PAGE 08H/ADDR 09H) .......................................................240
7/30/2009 PJ87F
Data Sheet BCM5328X
07/14/09
Broadcom Corporation
Document 5328X-DS200-R Page xvii
MEMORY ADDRESS 0/OFFSET Register (PAGE 08H/ADDR 10H) .................................. 241
MEMORY ADDRESS 1/OFFSET Register (PAGE 08H/ADDR 12H) .................................. 241
MEMORY DATA 0 Register (PAGE 08H/ADDR 20H)......................................................... 241
MEMORY DATA 1 Register (PAGE 08H/ADDR 28H)......................................................... 241
MEMORY DATA 2 Register (PAGE 08H/ADDR 30H)......................................................... 241
MEMORY DATA 3 Register (PAGE 08H/ADDR 38H)......................................................... 241
MEMORY DATA 4 Register (PAGE 08H/ADDR 40H)......................................................... 242
MEMORY DATA 5 Register (PAGE 08H/ADDR 48H)......................................................... 242
MEMORY DATA 6 Register (PAGE 08H/ADDR 50H)......................................................... 242
MEMORY DATA 7 Register (PAGE 08H/ADDR 58H)......................................................... 242
MEMORY KEY 0 Register (PAGE 08H/ADDR 80H) ........................................................... 242
MEMORY KEY 1 Register (PAGE 08H/ADDR 88H) ........................................................... 242
MEMORY KEY 2 Register (PAGE 08H/ADDR 90H) ........................................................... 243
MEMORY KEY 3 Register (PAGE 08H/ADDR 98H) ........................................................... 243
MEMORY KEY 4 Register (PAGE 08H/ADDR A0H).......................................................... 243
MEMORY KEY 5 Register (PAGE 08H/ADDR A8H).......................................................... 243
Memory Table Format Description............................................................................................... 244
ARL Table Format Description............................................................................................. 244
Multicast Table Format Description .................................................................................. 245
VLAN Table Format Description ....................................................................................... 246
Multiple Spanning Tree Table Format Description ............................................................ 247
CFP TCAM Key Data/Mask Table Format Description ..................................................... 248
CFP Action/policy RAM Format Description ..................................................................... 248
CFP Rate Meter RAM Format Description ........................................................................ 250
CFP In-band/Out-band Statistic RAM Format Description ................................................ 250
IVM Key TCAM Data/Mask Format Description ................................................................ 250
IVM Action RAM Format Description ................................................................................ 252
EVM Key TCAM Data/Mask Format Description .............................................................. 253
EVM Action RAM Format Description ............................................................................... 253
Ingress Rate Control Port Table Format Description ........................................................ 254
Egress Rate Control Port Table Format Description ......................................................... 255
1P-to-TCDP Port Mapping Table Format Description ....................................................... 256
TCDP-to-1P Port Mapping Table Format Description ....................................................... 256
Port Mask Table Format Description ................................................................................ 257
SA Learning Counter Configuration Table Format Description ......................................... 259
7/30/2009 PJ87F
BCM5328X Data Sheet
07/14/09
Broadcom Corporation
Page xviii Document 5328X-DS200-R
Multicast Group Virtual Port ID Mapping Table Format Description ..................................259
Virtual Port VID Mapping Table Format Description .........................................................260
Page 0AH: Congestion Control Registers..............................................................................................261
TC GROUP CONTROL Register (PAGE 0AH/ADDR 02H) .................................................263
TOTAL HYST COUNT Register (PAGE 0AH/ADDR 04H)...................................................263
TXQ HYST A COUNT Register (PAGE 0AH/ADDR 05H)....................................................264
TXQ HYST B COUNT Register (PAGE 0AH/ADDR 06H)....................................................264
FLOW CONTROL TRIGGER PORT CONTROL Register (PAGE 0AH/ADDR 08H)..........264
TOTAL PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 12H) .....................264
TOTAL CONGESTIOIN ON THRESHOLD Register (PAGE 0AH/ADDR 14H)....................264
TOTAL REGION STATUS Register (PAGE 0AH/ADDR 16H).............................................265
TXQ-Q0 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 18H)......265
TXQ-Q1 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 19H)......265
TXQ-Q2 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 1AH) .....265
TXQ-Q3 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 1BH) .....265
TXQ-Q4 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 1CH) .....266
TXQ-Q5 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 1DH) .....266
TXQ-Q6 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 1EH) .....266
TXQ-Q7 OVERSUBSCRIPTION ON THRESHOLD Register (PAGE 0AH/ADDR 1FH)......266
TXQ-Q0 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 20H) ...................266
TXQ-Q1 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 22H) ...................266
TXQ-Q2 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 24H) ...................267
TXQ-Q3 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 26H) ...................267
TXQ-Q4 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 28H) ..................267
TXQ-Q5 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 2AH)...................267
TXQ-Q6 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 2CH)...................267
TXQ-Q7 PROTECTION ON THRESHOLD Register (PAGE 0AH/ADDR 2EH)...................268
TXQ-Q0 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 30H)...................268
TXQ-Q1 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 32H)..................268
TXQ-Q2 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 34H)...................268
TXQ-Q3 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 36H)...................268
TXQ-Q4 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 38H)...................269
TXQ-Q5 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 3AH) ..................269
TXQ-Q6 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 3CH) ..................269
TXQ-Q7 CONGESTION ON THRESHOLD Register (PAGE 0AH/ADDR 3EH) ..................269
7/30/2009 PJ87F
Data Sheet BCM5328X
07/14/09
Broadcom Corporation
Document 5328X-DS200-R Page xix
QUEUE REGIOIN STATUS Register (PAGE 0AH/ADDR 40H-79H) .......................................... 270
Queue Region Status Register Bit Definitions ..................................................................... 271
Page 10H: PHY Information Registers ................................................................................................... 272
PHY ID HIGH Register (PAGE 10H/ADDR 04H)................................................................. 272
PHY ID LOW Register (PAGE 10H/ADDR 06H).................................................................. 272
Page 21H: CFP Control Registers........................................................................................................... 273
GLOBAL CFP CONTROL Register (PAGE 21H/ADDR 00H)............................................. 273
CFP ENABLE CONTROL Register (PAGE 21H/ADDR 20H)............................................. 273
VID RANGE CHECKER Register (PAGE 21H/ADDR 30H-3FH) ............................................... 274
VID Range Checker Register Bit Definitions....................................................................... 274
Page 22H: CFP User Define Control Registers...................................................................................... 275
CFP User Define Control Registers Bit Definitions.............................................................. 276
Page 28H: Default Port QoS Configuration Registers .......................................................................... 277
Default Port QoS Configuration Registers Bit Definitions .................................................... 277
DP CONTROL Register (PAGE 28H/ADDR E0H).............................................................. 278
Page 2CH: Switch Filtering Control Registers ...................................................................................... 279
GLOBAL MAC FRAMING FILTER CONTROL Register (PAGE 2CH/ADDR 00H) ........... 279
DOS ATTACK FILTER DROP CONTROL Register (PAGE 2CH/ADDR 20H).................. 280
Minimum TCP Header Size Register (PAGE 2CH/ADDR 22H)......................................... 281
Maximum ICMPv4 Size Register (PAGE 2CH/ADDR 24H)................................................. 281
Maximum ICMPv6 Size Register (PAGE 2CH/ADDR 28H)................................................. 281
DOS Attack Filter Event Register (PAGE 2CH/ADDR 30H) ................................................ 282
Page 30H: QoS Registers ........................................................................................................................ 284
QoS Control Register (PAGE 30H/ADDR 00H)................................................................... 285
TXQ Weight Quota Size Register (PAGE 30H/ADDR 02H) ............................................... 285
Trust S1P Control Register (PAGE 30H/ADDR 10H) ......................................................... 286
Trust C1P Control Register (PAGE 30H/ADDR 18H)......................................................... 286
Trust DSCP Control Register (PAGE 30H/ADDR 20H)...................................................... 287
TC to COS Mapping Register (PAGE 30H/ADDR 30H) .................................................... 287
DSCP to TC_DP Mapping – 0 Register (PAGE 30H/ADDR 40H) ....................................... 287
DSCP to TC_DP Mapping – 1 Register (PAGE 30H/ADDR 48H) ....................................... 288
DSCP to TC_DP Mapping – 2 Register (PAGE 30H/ADDR 50H) ....................................... 288
DSCP to TC_DP Mapping – 3 Register (PAGE 30H/ADDR 58H) ....................................... 289
DSCP to TC_DP Mapping – 4 Register (PAGE 30H/ADDR 60H) ....................................... 289
DSCP to TC_DP Mapping – 5 Register (PAGE 30H/ADDR 68H) ....................................... 290
7/30/2009 PJ87F
BCM5328X Data Sheet
07/14/09
Broadcom Corporation
Page xx Document 5328X-DS200-R
DSCP to TC_DP Mapping – 6 Register (PAGE 30H/ADDR 70H)........................................290
DSCP to TC_DP Mapping – 7 Register (PAGE 30H/ADDR 78H)........................................291
TC_DP to DSCP Mapping – 0 Register (PAGE 30H/ADDR 80H).......................................291
TC_DP to DSCP Mapping – 1 Register (PAGE 30H/ADDR 88H).......................................291
TC_DP to DSCP Mapping – 2 Register (PAGE 30H/ADDR 90H).......................................292
TC_DP to DSCP Mapping – 3 Register (PAGE 30H/ADDR 98H).......................................292
TC_DP to DSCP Mapping – 4 Register (PAGE 30H/ADDR A0H) ......................................292
TC_DP to DSCP Mapping – 5 Register (PAGE 30H/ADDR A8H) ......................................293
TC_DP to DSCP Mapping – 6 Register (PAGE 30H/ADDR B0H) ......................................293
TC_DP to DSCP Mapping – 7 Register (PAGE 30H/ADDR B8H) ......................................293
QOS_REASON_CODE Register (PAGE 30H/ADDR C0H) ................................................294
TXQ Backpressure IMP Port Control Register (PAGE 30H/ADDR D0H)............................295
TXQ Backpressure GE0 Port Control Register (PAGE 30H/ADDR D1H)............................295
TXQ Backpressure GE1 Port Control Register (PAGE 30H/ADDR D2H)...........................295
TXQ Backpressure GE2 Port Control Register (PAGE 30H/ADDR D3H)...........................296
TXQ Backpressure GE3 Port Control Register (PAGE 30H/ADDR D4H)...........................296
Page 31H: TRUNK Registers ...................................................................................................................297
Global Trunk Control Register (PAGE 31H/ADDR 00H) ......................................................298
Trunk Group 0 Port Register (PAGE 31H/ADDR 10H) ........................................................298
Trunk Group 1 Port Register (PAGE 31H/ADDR 18H) ........................................................298
Trunk Group 2 Port Register (PAGE 31H/ADDR 20H) ........................................................299
Trunk Group 3 Port Register (PAGE 31H/ADDR 28H) ........................................................299
Trunk Group 4 Port Register (PAGE 31H/ADDR 30H) ........................................................299
Trunk Group 5 Port Register (PAGE 31H/ADDR 38H) ........................................................300
Trunk Group 6 Port Register (PAGE 31H/ADDR 40H) ........................................................300
Trunk Group 7 Port Register (PAGE 31H/ADDR 48H) ........................................................301
Trunk Group 8 Port Register (PAGE 31H/ADDR 50H) ........................................................301
Trunk Group 9 Port Register (PAGE 31H/ADDR 58H) ........................................................301
Trunk Group 10 Port Register (PAGE 31H/ADDR 60H) ......................................................302
Trunk Group 11 Port Register (PAGE 31H/ADDR 68H) ......................................................302
Trunk Group 12 Port Register (PAGE 31H/ADDR 70H) ......................................................303
Trunk Group 13 Port Register (PAGE 31H/ADDR 78H) ......................................................303
Page 34H: VLAN Registers ......................................................................................................................304
VLAN GLOBAL CONTROL Register (PAGE 34H/ADDR 00H)...........................................304
VLAN BYPASS CONTROL Register (PAGE 34H/ADDR 01H)..........................................304
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