BCM53212M 用户手册：博通高性能管理型交换芯片

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"BCM53212M-DS302是博通公司的一款管理型交换芯片的手册，详细介绍了其功能、特点以及技术规格。该芯片是基于BCM5324的第九代RoboSwitch设计，适用于高速交换系统，提供24个快速以太网端口和4个千兆以太网接口。" 博通BCM53212M是一款高性能的集成式网络交换芯片，旨在实现与IEEE 802.3和IEEE 802.3x标准的全面兼容，确保与各种标准的以太网和快速以太网设备无缝协作。它集成了关键的网络组件，如包缓冲区、物理层收发器（PHY）、媒体访问控制器（MACs）和非阻塞交换架构，以提供高效、稳定的网络连接。该芯片的主要特点包括： 1. **24个快速以太网端口（10/100Mbps）**：每个端口都支持全双工10Base-T和100Base-TX模式，并且具有高级电缆诊断功能，可在Cat3、4或5类非屏蔽双绞线（UTP）上运行10Base-T，以及在Cat5 UTP上运行100Base-TX。 2. **4个千兆以太网接口**：通过GMII/RGMII/TBI接口提供，可以实现高速网络通信。 3. **非阻塞交换架构**：确保数据流畅无阻，避免网络拥塞，提高网络效率。 4. **MAC控制PAUSE帧支持**：允许网络设备根据需要暂停流量传输，以防止过载。 5. **自动协商功能**：自动检测并配置连接的网络设备的最佳速度和双工模式。 6. **地址管理**：处理MAC地址学习和转发，确保数据包正确发送到目的地。 BCM53212M的这些特性使其成为企业级网络、数据中心和家庭网络应用的理想选择，能够提供高效能、低延迟的以太网连接。其集成化设计减少了硬件成本，简化了系统设计，同时保持了强大的网络性能和可靠性。这款芯片的详细使用说明和寄存器说明对于开发者和网络管理员来说是宝贵的参考资料，帮助他们充分利用其功能并进行故障排查。

Broadcom Confidential

Table of Contents BCM53212M Data Sheet

BROADCOM

July 28, 2011 • 53212M-DS302-R Page 16

Reserved Bit..................................................................................................................................331

MF Preamble Suppression ............................................................................................................331

Auto-Negotiation Complete .........................................................................................................331

Remote Fault ................................................................................................................................331

Auto-Negotiation Capability .........................................................................................................331

Link Status.....................................................................................................................................331

Jabber Detect................................................................................................................................332

Extended Capability ......................................................................................................................332

PHY Identifier Registers (Page A0h–B7h/Addr 04h–07h) ....................................................................333

Auto-Negotiation Advertisement Register (Page A0h–B7h/Addr 08h–09h) .......................................333

Next Page......................................................................................................................................333

Remote Fault ................................................................................................................................333

Reserved Bits ................................................................................................................................334

Pause Operation for Full-Duplex Links.......................................................................................... 334

Advertisement Bits .......................................................................................................................334

Selector Field ................................................................................................................................334

Auto-Negotiation Link Partner Ability Register (Page A0h–B7h/Addr 0Ah–0Bh) ................................334

Next Page......................................................................................................................................335

Acknowledge ................................................................................................................................335

Remote Fault ................................................................................................................................335

Reserved Bits ................................................................................................................................335

Pause ............................................................................................................................................335

Advertisement Bits .......................................................................................................................335

Selector Field ................................................................................................................................335

Auto-Negotiation Expansion Register (Page A0h–B7h/Addr 0Ch–0Dh) ..............................................335

Parallel Detection Fault ................................................................................................................336

Link Partner Next Page Able .........................................................................................................336

Page Received...............................................................................................................................336

Link Partner Auto-Negotiation Able .............................................................................................336

Auto-Negotiation Next Page Register (Page A0h–B7h/Addr 0Eh–0Fh) ...............................................337

Next Page......................................................................................................................................337

Message Page ...............................................................................................................................337

Acknowledge 2 .............................................................................................................................337

Toggle ...........................................................................................................................................337

Message Code Field ......................................................................................................................337

Broadcom Confidential

Table of Contents BCM53212M Data Sheet

BROADCOM

July 28, 2011 • 53212M-DS302-R Page 17

Unformatted Code Field ...............................................................................................................337

Link Partner Next Page Register (Page A0h–B7h/Addr 10h–11h) .......................................................338

Next Page......................................................................................................................................338

Message Page ...............................................................................................................................338

Acknowledge 2 .............................................................................................................................338

Toggle ...........................................................................................................................................338

Message Code Field ......................................................................................................................338

Unformatted Code Field ...............................................................................................................338

Page D8h–DAh: External PHY Registers.....................................................................................................339

Global Registers..........................................................................................................................................341

SPI Data I/O Register............................................................................................................................341

SPI Status Register ...............................................................................................................................341

Page Register .......................................................................................................................................342

Section 9: Electrical Characteristics................................................................................ 343

Absolute Maximum Ratings.......................................................................................................................343

Recommended Operating Conditions........................................................................................................343

Electrical Characteristics ............................................................................................................................344

Section 10: BCM53212M Timing Characteristics ............................................................ 346

Reset and Clock Timing ..............................................................................................................................346

LED Timing ..................................................................................................................................................347

MII Input Timing .........................................................................................................................................348

RvMII Input Timing .....................................................................................................................................349

MII Output Timing ......................................................................................................................................350

RvMII Output Timing ..................................................................................................................................351

RGMII Interface Timing ..............................................................................................................................352

RGMII Output Timing (Normal Mode) .................................................................................................352

RGMII Input Timing (Normal Mode) ....................................................................................................353

GMII Interface Timing.................................................................................................................................354

GMII Interface Output Timing..............................................................................................................354

GMII Interface Input Timing.................................................................................................................354

TBI Interface Timing ...................................................................................................................................356

TBI Interface Output Timing ................................................................................................................356

TBI Interface Input Timing ...................................................................................................................356

SPI Timing ...................................................................................................................................................358

EEPROM Timing ..........................................................................................................................................360

Management Data Interface......................................................................................................................360

Broadcom Confidential

List of Figures BCM53212M Data Sheet

BROADCOM

July 28, 2011 • 53212M-DS302-R Page 19

List of Figures

Figure 1: Functional Block Diagram....................................................................................................................2

Figure 2: Shaping-Scheduling Structure of Each Egress port............................................................................38

Figure 3: First Level QoS Resolution Tree.........................................................................................................40

Figure 4: Final level QoS Resolution Tree .........................................................................................................42

Figure 5: VLAN Resolution Tree........................................................................................................................44

Figure 6: NNI to NNI Tag Handling ...................................................................................................................46

Figure 7: UNI to NNI .........................................................................................................................................47

Figure 8: NNI to UNI .........................................................................................................................................48

Figure 9: UNI to UNI .........................................................................................................................................49

Figure 10: Non_Double Tagging Mode UNI to UNI ..........................................................................................50

Figure 11: Link Aggregation..............................................................................................................................51

Figure 12: Ingress Bucket Flow.........................................................................................................................53

Figure 13: Mirror Filter Flow ............................................................................................................................55

Figure 14: BCM53212M Address Table Organization.......................................................................................58

Figure 15: CFP Engines .....................................................................................................................................66

Figure 16: Standard Packet Format ..................................................................................................................69

Figure 17: Cable Analyzer Flow Chart...............................................................................................................87

Figure 18: Broadcom-Tagged Packet Encapsulation Format............................................................................89

Figure 19: MAC-to-MAC MII Connection........................................................................................................104

Figure 20: SPI Serial Interface Write Operation .............................................................................................108

Figure 21: SPI Serial Interface Read Operation ..............................................................................................108

Figure 22: Normal SPI Mode Read Flow Chrt .................................................................................................110

Figure 23: Normal SPI Mode Write Flow Chart ..............................................................................................111

Figure 24: Serial EEPROM Connection ...........................................................................................................112

Figure 25: Pseudo PHY MII Register Definitions.............................................................................................117

Figure 26: Pseudo PHY MII Register 16: Register Set Access Control Bit Definition ......................................118

Figure 27: Pseudo PHY MII Register 17: Register Set Read/Write Control Bit Definition ..............................118

Figure 28: Pseudo PHY MII Register 18: Register Access Status Bit Definition ..............................................118

Figure 29: Pseudo PHY MII Register 24: Access Register Bit Definition .........................................................119

Figure 30: Pseudo PHY MII Register 25: Access Register Bit Definition .........................................................119

Figure 31: Pseudo PHY MII Register 26: Access Register Bit Definition .........................................................119

Figure 32: Pseudo PHY MII Register 27: Access Register Bit Definition .........................................................120

Figure 33: Read Access to the Register Set Via the Pseudo PHY (Phyad = 11110) MDC/MDIO Path.............121

Figure 34: Write Access to the Register Set Via the Pseudo PHY (Phyad = 11110) MDC/MDIO Path............122

Figure 35: Serial LED Shift Sequence LEDMODE[2:0] = ‘000’ .........................................................................124

Broadcom Confidential

List of Figures BCM53212M Data Sheet

BROADCOM

July 28, 2011 • 53212M-DS302-R Page 20

Figure 36: Bicolor LINK/ACT LED Scheme.......................................................................................................125

Figure 37: BCM53212 LED Register Structure Diagram..................................................................................128

Figure 38: Partial Example External Circuit for Serial LED Mode (LEDMODE[2:0]=’000’) ..............................129

Figure 39: External PNP for 1.2V Voltage Regulators.....................................................................................131

Figure 40: External PNP for 2.5V Voltage Regulators.....................................................................................131

Figure 41: 400-PBGA Ball Location Diagram (Top View) ................................................................................150

Figure 42: Reset and Clock Timing .................................................................................................................346

Figure 43: Serial LED Timing ...........................................................................................................................347

Figure 44: MII Input Timing ............................................................................................................................348

Figure 45: RvMII Input Timing ........................................................................................................................349

Figure 46: MII Output Timing .........................................................................................................................350

Figure 47: RvMII Output Timing .....................................................................................................................351

Figure 48: RGMII Output Timing (Normal Mode)...........................................................................................352

Figure 49: RGMII Input Timing (Normal Mode)..............................................................................................353

Figure 50: GMII Output Timing.......................................................................................................................354

Figure 51: GMII Input Timing..........................................................................................................................354

Figure 52: TBI Output Timing .........................................................................................................................356

Figure 53: TBI Input Timing ............................................................................................................................356

Figure 54: SPI Timing, SS

Asserted During SCK High.......................................................................................358

Figure 55: SPI Timing, SS

Asserted During SCK Low .......................................................................................358

Figure 56: EEPROM Timing.............................................................................................................................360

Figure 57: Management Data Interface .........................................................................................................360

Figure 58: 400-PBGA Package Outline Drawing .............................................................................................364

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