"TI TUSB3410 串口转USB产品手册及技术资料"

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产品描述：串口转USB是一种功能强大的设备，它能够将串行接口和USB接口相互转换，使得串行设备能够通过USB接口与计算机进行通信。TI-TUSB3410是一款高性能的串口转USB解决方案，具有多种特色功能和广泛的应用领域。这款产品具有先进的技术和可靠的性能，在各个行业中得到了广泛的应用。 TI-TUSB3410的技术参数和特点设计使其成为一款适应性广泛的串口转USB解决方案。首先，它支持多种串行接口协议，如RS-232、RS-422和RS-485等，能够满足不同类型的串行设备的连接需求。其次，它支持高速USB 2.0接口，数据传输速率可达12Mbps，确保了数据的快速传输和稳定性。此外，它还具备多种电源管理模式，可以根据应用需求选择适当的模式以达到节能和延长电池寿命的目的。此外，TI-TUSB3410还具备丰富的接口保护功能，如过压保护、过流保护、瞬态电压抑制等，确保了设备的安全和可靠性。 TI-TUSB3410的高可靠性使得它在各个行业中得到广泛应用。首先，它可以广泛应用于工业自动化领域。随着工业自动化的快速发展，许多设备和控制系统使用串行接口与计算机连接，而现代计算机通常只配备USB接口。TI-TUSB3410能够解决这一矛盾，将串行设备快速、稳定地连接到计算机，实现数据的互通和控制的逻辑。其次，它还可以应用于通信设备和网络设备。在通信和网络领域，串口设备的连接非常常见。TI-TUSB3410可以轻松连接串行设备和计算机，实现数据的传输和通信的效果。再次，它还可以被应用于医疗设备和仪器仪表。在医疗行业和实验室中，很多设备需要与计算机进行通信，例如心电图仪、血压计等。TI-TUSB3410能够将这些设备连接到计算机，实现数据的传输和控制，提高了医疗设备和仪器仪表的便利性和效率。除了以上行业，TI-TUSB3410还可以应用于安防设备、智能家居、汽车电子等领域。在安防领域，串行设备的连接是必不可少的，TI-TUSB3410可以提供可靠的连接和数据传输。在智能家居中，许多设备需要和计算机或智能手机进行通信，TI-TUSB3410可以提供高速、稳定的连接，实现智能家居系统的功能。在汽车电子领域，现代汽车中的许多设备和系统都是通过串行接口与计算机相连接，TI-TUSB3410可以将这些设备连接到汽车的娱乐系统或操作系统中，实现控制和数据传输的需求。总的来说，TI-TUSB3410是一款功能强大、性能稳定、可靠性高的串口转USB解决方案。它的多种特色功能和广泛应用领域使得它成为许多行业中的理想选择，为用户提供了稳定、高效的数据传输和控制解决方案。无论是工业自动化、通信设备、医疗仪器还是安防设备等领域，TI-TUSB3410都能够提供可靠的连接和数据传输，满足不同行业及应用的需求。

TUSB3410, TUSB3410I

SLLS519J –MARCH 2002–REVISED JULY 2017

www.ti.com

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Product Folder Links: TUSB3410

5.4 Processor Subsystems

5.4.1 DMA Controller

5.4.1.1 Bulk Data I/O Using the EDB

The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer

parameters for IN and OUT transactions (IN and OUT are with respect to host). In this discussion, it is

assumed that:

• The MCU initialized the EDBs

• DMA-continuous mode is being used

• Double buffering is being used

• The X/Y toggle is controlled by the UBM

5.4.1.1.1 IN Transaction (TUSB3410 to Host)

1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

– DMACSR3: Defines the transaction time-out value.

– DMACDR3: Defines the IEDB being used and the DMA mode of operation (continuous mode).

Once this register is set with EN = 1, the transfer starts.

2. The DMA transfers data from the UART to the X buffer. When a block of 64 bytes is transferred, the

DMA updates the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to

the UBM that the X buffer is ready to be transferred to host). The UBM starts X-buffer transfer to host

using the byte-count value in the input endpoint byte count register and toggles the X/Y bit. The DMA

continues transferring data from a device to Y buffer. At the end of the block transfer, the DMA updates

the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM that

the Y buffer is ready to be transferred to host). The DMA continues the transfer from the device to

host, alternating between X and Y buffers without MCU intervention.

3. Transfer termination: The DMA/UBM continues the data transfer, alternating between the X and Y

buffers. Termination of the transfer can happen under the following conditions:

– Stop Transfer: The host notifies the MCU (through control-end-point) to stop the transfer. Under

this condition, the MCU sets bit 7 (EN) to 0 in the DMACDR register.

– Partial Packet: The device receiver has no data to be transferred to host. Under this condition, the

byte-count value is less than 64 when the transaction timer time-out occurs. When the DMA detects

this condition, it sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, updates

the byte count and NAK bit in the input endpoint byte count register, and interrupts the MCU. The

UBM transfers the partial packet to host.

– Buffer Overrun: The host is busy, X and Y buffers are full (X-NAK = 0 and Y-NAK = 0), and the

DMA cannot write to these buffers. The transaction time-out stops the DMA transfer, the DMA sets

bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 1 in the DMACSR3 register, and interrupts the MCU.

– UART Error Condition: When receiving from a UART, a receiver-error condition stops the DMA

and sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, but the EN bit remains

set at 1. Therefore, the DMA does not interrupt the MCU. However, the UART generates a status

interrupt, notifying the MCU that an error condition has occurred.

TUSB3410

SIN

RTS

SOUT

CTS

External Device

SOUT

CTS

SIN

RTS

TUSB3410, TUSB3410I

www.ti.com

SLLS519J –MARCH 2002–REVISED JULY 2017

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Product Folder Links: TUSB3410

5.4.2.1.2 Hardware Flow Control

Figure 5-7 illustrates the connection necessary to achieve hardware flow control. The CTS and RTS

signals are provided for this purpose. Auto CTS and auto RTS (and Xon/Xoff) can be enabled and

disabled independently by programming the UART flow control register (FCRL).

Figure 5-7. Auto Flow Control Interconnect

5.4.2.1.3 Auto RTS (Receiver Control)

In this mode, the RTS output terminal signals the receiver-FIFO status to an external device. The RTS

output signal is controlled by the high- and low-level marks of the FIFO. When the high-level mark is

reached, RTS goes high, signaling to an external sending device to halt its transfer. Conversely, when the

low-level mark is reached, RTS goes low, signaling to an external sending device to resume its transfer.

Data transfer from the FIFO to the X and Y buffer is performed by the DMA controller. See

Section 5.4.1.1.1 for DMA transfer-termination condition.

5.4.2.1.4 Auto CTS (Transmitter Control)

In this mode, the CTS input terminal controls the transfer from internal buffer (X or Y) to the TDR. When

the DMA controller transfers data from the Y buffer to the TDR and the CTS input terminal goes high, the

DMA controller is suspended until CTS goes low. Meanwhile, the UBM is transferring data from the host to

the X buffer. When CTS goes low, the DMA resumes the transfer. Data transfer continues alternating

between the X and Y buffers, without MCU intervention. See Section 5.4.1.1.2 for DMA transfer-

termination condition.

5.4.2.1.5 Xon/Xoff Receiver Flow Control

To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows:

MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the Xon/Xoff bytes are transmitted to an external

sending device to control the transmission of the device. When the high-level mark (of the FIFO) is

reached, the Xoff byte is transmitted, signaling to an external sending device to halt its transfer.

Conversely, when the low-level mark is reached, the Xon byte is transmitted, signaling to an external

sending device to resume its transfer. The data transfer from the FIFO to X and Y buffer is performed by

the DMA controller.

5.4.2.1.6 Xon/Xoff Transmit Flow Control

To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows:

MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the incoming data are compared to the XON and

XOFF registers. If a match to XOFF is detected, the DMA is paused. If a match to XON is detected, the

DMA resumes. Meanwhile, the UBM is transferring data from the host to the X-buffer. The MCU does not

switch the buffers unless the Y buffer is empty and the X-buffer is full. When Xon is detected, the DMA

resumes the transfer.

TUSB3410, TUSB3410I

SLLS519J –MARCH 2002–REVISED JULY 2017

www.ti.com

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Product Folder Links: TUSB3410

5.4.3 I

C Port

5.4.3.1 Random-Read Operation

A random read requires a dummy byte-write sequence to load in the data word address. Once the device-

address word and the data-word address are clocked out and acknowledged by the device, the MCU

starts a current-address sequence. The following describes the sequence of events to accomplish this

transaction.

5.4.3.1.1 Device Address + EPROM [High Byte]

1. The MCU clears bit 1 (SRD) within the I2CSTA register. This forces the I

C controller not to generate a

stop condition after the contents of the I2CDAI register are received.

2. The MCU clears bit 0 (SWR) within the I2CSTA register. This forces the I

C controller not to generate

a stop condition after the contents of the I2CDAO register are transmitted.

3. The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation)

4. The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the

transfer on the SDA line).

5. Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing data to the

I2CDAO register.

6. The contents of the I2CADR register are transmitted to EEPROM (preceded by start condition on

SDA).

7. The contents of the I2CDAO register are transmitted to EEPROM (EPROM address).

8. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

has been transmitted.

9. A stop condition is not generated.

5.4.3.1.2 EPROM [Low Byte]

1. The MCU writes the low byte of the EEPROM address into the I2CDAO register.

2. Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing to the I2CDAO

3. The contents of the I2CDAO register are transmitted to the device (EEPROM address).

4. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register

has been transmitted.

5. This completes the dummy write operation. At this point, the EEPROM address is set and the MCU

can do either a single- or a sequential-read operation.

5.4.3.2 Current-Address Read Operation

When the EEPROM address is set, the MCU can read a single byte by executing the following steps:

1. The MCU sets bit 1 (SRD) in the I2CSTA register to 1. This forces the I

C controller to generate a stop

condition after the I2CDAI-register contents are received.

2. The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).

3. The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on SDA line).

4. Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).

5. The contents of the I2CADR register are transmitted to the device (preceded by start condition on

SDA).

6. The data from EEPROM are latched into the I2CDAI register (stop condition is transmitted).

7. Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that the data are available.

8. The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.

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